NXP Semiconductors LPC43 Series User Manual

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NXP Semiconductors LPC43 Series User Manual Manual pdf 998 page image

UM10503 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.User manual Rev. 1.3 — 6 July 2012 998 of 1269NXP Semiconductors UM10503Chapter 38: LPC43xx UART138.6.15 UART1 RS485 Control registerThe RS485CTRL register controls the configuration of the UART in RS-485/EIA-485mode.Table 864: UART1 Transmit Enable Register (TER - address 0x4008 2030) bit descriptionBit Symbol Description Reset value6:0 - Reserved, user software should not write ones to reserved bits. The value read from areserved bit is not defined.NA7 TXEN Transmit enable bit.When this bit is 1, as it is after a Reset, data written to the THR is output on the TXD pin assoon as any preceding data has been sent. If this bit cleared to 0 while a character is beingsent, the transmission of that character is completed, but no further characters are sent untilthis bit is set again. In other words, a 0 in this bit blocks the transfer of characters from theTHR or TX FIFO into the transmit shift register. Software can clear this bit when it detectsthat the a hardware-handshaking TX-permit signal (CTS) has gone false, or with softwarehandshaking, when it receives an XOFF character (DC3). Software can set this bit againwhen it detects that the TX-permit signal has gone true, or when it receives an XON (DC1)character.131:8 - Reserved, user software should not write ones to reserved bits. The value read from areserved bit is not defined.NATable 865: UART1 RS485 Control register (RS485CTRL - address 0x4008 204C) bit descriptionBit Symbol Value Description Reset value0 NMMEN Multidrop mode select. 00 RS-485/EIA-485 Normal Multidrop Mode (NMM) is disabled.1 RS-485/EIA-485 Normal Multidrop Mode (NMM) is enabled. In this mode, anaddress is detected when a received byte causes the UART to set the parity errorand generate an interrupt.1 RXDIS Receive enable. 00 The receiver is enabled.1 The receiver is disabled.2 AADEN Auto Address Detect enable. 00 Auto Address Detect (AAD) is disabled.1 Auto Address Detect (AAD) is enabled.3 SEL Direction control. 00 If direction control is enabled (bit DCTRL = 1), pin RTS is used for direction control.1 If direction control is enabled (bit DCTRL = 1), pin DTR is used for direction control.4 DCTRL Direction control enable. 00 Disable Auto Direction Control.1 Enable Auto Direction Control.5 OINV Polarity.This bit reverses the polarity of the direction control signal on the RTS (or DTR) pin.00 The direction control pin will be driven to logic ‘0’ when the transmitter has data tobe sent. It will be driven to logic ‘1’ after the last bit of data has been transmitted.1 The direction control pin will be driven to logic ‘1’ when the transmitter has data tobe sent. It will be driven to logic ‘0’ after the last bit of data has been transmitted.31:6 - - Reserved, user software should not write ones to reserved bits. The value readfrom a reserved bit is not defined.NA