NXP Semiconductors LPC43 Series User Manual

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NXP Semiconductors LPC43 Series User Manual Manual pdf 948 page image

UM10503 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.User manual Rev. 1.3 — 6 July 2012 948 of 126937.1 How to read this chapterThe USART0/2/3 controllers are available on all LPC43xx parts.37.2 Basic configurationThe USART0/2/3 are configured as follows:• See Table 819 for clocking and power control.• The USART0/2/3 are reset by the UART0/2/3_RST (reset #44/46/47).• The USART0/2/3 interrupts are connected to slots # 24/26/27 in the NVIC.• For connecting the USART0/2/3 receive and transmit lines to the GPDMA, use theDMAMUX register in the CREG block (see Table 46) and enable the GPDMA channelin the DMA Channel Configuration registers (Section 19.6.20).• The internal USART transmit/receive active signals (USARTx TX/RX) are connectedto the GIMA (see Table 148). These signals are driven when data are transmitted orreceived and can be used to trigger any of the timers or the SCT.• In synchronous mode, set the clock frequency on pin U0/2/3_UCLK to 6  BASE_UART0/2/3_CLK.37.3 Features• 16-byte receive and transmit FIFOs.• Register locations conform to ‘550 industry standard.• Receiver FIFO trigger points at 1, 4, 8, and 14 bytes.• Built-in baud rate generator.• UART mode allows for implementation of either software or hardware flow control.• RS-485/EIA-485 9-bit mode support with output enable.• Support for synchronous mode UART (USART).• IrDA interface (USART3 only).• DMA support.UM10503Chapter 37: LPC43xx USART0_2_3Rev. 1.3 — 6 July 2012 User manualTable 819. USART0/2/3 clocking and power controlBase clock Branch clock OperatingfrequencyUSART0 clock to register interface BASE_M4_CLK CLK_M4_UART0 up to 204 MHzUSART0 peripheral clock (PCLK) BASE_UART0_CLK CLK_APB0_UART0 up to 204 MHzUSART2 clock to register interface BASE_M4_CLK CLK_M4_UART2 up to 204 MHzUSART2 peripheral clock (PCLK) BASE_UART2_CLK CLK_APB2_UART2 up to 204 MHzUSART3 clock to register interface BASE_M4_CLK CLK_M4_UART3 up to 204 MHzUSART3 peripheral clock (PCLK) BASE_UART3_CLK CLK_APB2_UART3 up to 204 MHz