NXP Semiconductors LPC43 Series User Manual

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NXP Semiconductors LPC43 Series User Manual Manual pdf 832 page image

UM10503 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.User manual Rev. 1.3 — 6 July 2012 832 of 1269NXP Semiconductors UM10503Chapter 28: LPC43xx State Configurable Timer (SCT)28.6.22 SCT capture control registers 0 to 15 (REGMODEn bit = 1)If UNIFY = 1 in the CONFIG register, only the _L bits are used.If UNIFY = 0 in the CONFIG register, this register can be written to as two registersCAPCTRLn_L (address 0x4000 4100 to 0x4000 413C) and CAPCTRLn_H (address0x4000 4102 to 0x4000 413E). Both the L and H registers can be read or writtenindividually or in a single 32-bit read or write operation.Each Capture Control register (L, H, or unified 32-bit) controls which events load thecorresponding Capture register from the counter.28.6.23 SCT event state mask registers 0 to 15Each event has one associated SCT event state mask register that allow this event tohappen in one or more states of the counter selected by the HEVENT bit in thecorresponding EVCTRLn register.An event n is disabled when its EVSTATEMSKn register contains all zeros, since it ismasked regardless of the current state.In simple applications that do not use states, write 0x01 to this register to enable an event.Since the state always remains at its reset value of 0, writing 0x01 effectively permanentlystate-enables this event.28.6.24 SCT event control registers 0 to 15This register defines the conditions for event n to occur, other than the state variablewhich is defined by the state mask register. Most events are associated with a particularcounter (high, low, or unified), in which case the event can depend on a match to thatregister. The other possible ingredient of an event is a selected input or output signal.Table 669. SCT capture control registers 0 to 15 (CAPCTRL- address 0x4000 0200(CAPCTRL0) to 0x4000 023C (CAPCTRL15)) bit description (REGMODEn bit = 1)Bit Symbol Description Resetvalue15:0 CAPCONn_L If bit m is one, event m causes the CAPn_L (UNIFY = 0) or theCAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1= bit 1,..., event 15 = bit 15).031:16 CAPCONn_H If bit m is one, event m causes the CAPn_H (UNIFY = 0)register to be loaded (event 0 = bit 16, event 1 = bit 17,..., event15 = bit 31).0Table 670. SCT event state mask registers 0 to 15 (EVSTATEMSK - addresses 0x4000 0300(EVSTATEMSK0) to 0x4000 0378 (EVSTATEMSK15)) bit descriptionBit Symbol Description Resetvalue31:0 STATEMSKn If bit m is one, event n (n= 0 to 15) happens in state m of thecounter selected by the HEVENT bit (m = state number; state 0= bit 0, state 1= bit 1,..., state 31 = bit 31).0