UM10503 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.User manual Rev. 1.3 — 6 July 2012 273 of 1269NXP Semiconductors UM10503Chapter 14: LPC43xx Pin configurationPF_3 E10 - 170 [3] N;PU- R — Function reserved.I U3_RXD — Receiver input for USART3.I/O SSP0_MOSI — Master Out Slave in for SSP0.- R — Function reserved.I/O GPIO7[18] — General purpose digital input/output pin.- R — Function reserved.I/O SGPIO2 — General purpose digital input/output pin.- R — Function reserved.PF_4 D10 L8 172 [3] O;PUI/O SSP1_SCK — Serial clock for SSP1.I GP_CLKIN — General purpose clock input to the CGU.O TRACECLK — Trace clock.- R — Function reserved.- R — Function reserved.- R — Function reserved.O I2S0_TX_MCLK — I2S transmit master clock.I/O I2S0_RX_SCK — I2S receive clock. It is driven by the master andreceived by the slave. Corresponds to the signal SCK in the I 2S-busspecification.PF_5 E9 - 190 [6] N;PU- R — Function reserved.I/O U3_UCLK — Serial clock input/output for USART3 in synchronousmode.I/O SSP1_SSEL — Slave Select for SSP1.O TRACEDATA[0] — Trace data, bit 0.I/O GPIO7[19] — General purpose digital input/output pin.- R — Function reserved.I/O SGPIO4 — General purpose digital input/output pin.- R — Function reserved.AI ADC1_4 — ADC1, input channel 4. Configure the pin as GPIO inputand use the ADC function select register in the SCU to select theADC.Table 130. LPC4357/53 Pin description …continuedPin nameLBGA256TFBGA180LQFP208Reset state[2]TypeDescription