NXP Semiconductors LPC43 Series User Manual

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NXP Semiconductors LPC43 Series User Manual Manual pdf 305 page image

UM10503 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.User manual Rev. 1.3 — 6 July 2012 305 of 126916.1 How to read this chapterRemark: The VADC block is not available on the LPC4350/30/20/10 and LPC4357/53.16.2 Basic configurationThe GIMA is configured as follows:• See Table 147 for clocking and power control.• The GIMA is reset by the BUS_RST (reset #8 ). Do not reset the GIMA during normaloperation• The GIMA outputs are connected to the timer, SCT, ADC, and event routerperipherals (see Figure 33).• To configure the GIMA inputs for the timers and SCT, set the CTOUTCTRL bit inCREG6 (Table 50). This bit controls whether the SCT outputs are ORed with the timermatch outputs or whether the SCT outputs only are used.16.3 General descriptionThe Global Input Multiplexer Array (GIMA) connects events to various event triggeredperipherals such as the ADCs, the SCT, or the timers.Each output of the GIMA is connected to a peripheral function (for example, a timercapture input or an ADC conversion trigger input) and configured through one register,which selects the event triggers and configures the clock synchronization.For example, an ADC conversion can be triggered on either an SCT output or a timermatch output. To select the trigger event, use GIMA output 28 which is connected to theADC0 and ADC1 start0 conversion inputs. The corresponding GIMA output registerADCSTART0_IN selects SCT output 15 or the match output 0 of timer 0 as conversiontriggers (see Table 148).16.3.1 GIMA event input selectionEvents that can trigger a peripheral function (e.g. an ADC conversion or a timer capture)can be selected from the following sources:• Timer capture pins• SCT input pins• Timer0/1/2/3 match outputs• SCT outputsUM10503Chapter 16: LPC43xx Global Input Multiplexer Array (GIMA)Rev. 1.3 — 6 July 2012 User manualTable 147. GIMA clocking and power controlBase clock Branch clock MaximumfrequencyClock to GIMA register interface BASE_M4_CLK CLK_M4_BUS 204 MHz