NXP Semiconductors LPC43 Series User Manual

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NXP Semiconductors LPC43 Series User Manual Manual pdf 982 page image

UM10503 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.User manual Rev. 1.3 — 6 July 2012 982 of 1269NXP Semiconductors UM10503Chapter 38: LPC43xx UART1The UART1 receiver block, RX, monitors the serial input line, RXD, for valid input. TheUART1 RX Shift Register (RSR) accepts valid characters via RXD. After a valid characteris assembled in the RSR, it is passed to the UART1 RX Buffer Register FIFO to awaitaccess by the CPU or host via the generic host interface.The UART1 transmitter block, TX, accepts data written by the CPU or host and buffers thedata in the UART1 TX Holding Register FIFO (THR). The UART1 TX Shift Register (TSR)reads the data stored in the THR and assembles the data to transmit via the serial outputpin, TXD1.The UART1 Baud Rate Generator block, BRG, generates the timing enables used by theUART1 TX and RX blocks. The BRG clock input source is the APB clock (PCLK). Themain clock is divided down per the divisor specified in the DLL and DLM registers. Thisdivided down clock is a 16x oversample clock, NBAUDOUT.The modem interface contains registers MCR and MSR. This interface is responsible forhandshaking between a modem peripheral and the UART1.The interrupt interface contains registers IER and IIR. The interrupt interface receivesseveral one clock wide enables from the TX and RX blocks.Status information from the TX and RX is stored in the LSR. Control information for the TXand RX is stored in the LCR.