UM10503 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.User manual Rev. 1.3 — 6 July 2012 864 of 1269NXP Semiconductors UM10503Chapter 30: LPC43xx Motor Control PWM (MOTOCONPWM)The MCPWM includes 3 channels, each of which controls a pair of outputs that in turn cancontrol something off-chip, like one set of coils in a motor. Each channel includes aTimer/Counter (TC) register that is incremented by a processor clock (timer mode) or byan input pin (counter mode).Each channel has a Limit register that is compared to the TC value, and when a matchoccurs the TC is “recycled” in one of two ways. In “edge-aligned mode” the TC is reset to0, while in “centered mode” a match switches the TC into a state in which it decrements oneach processor clock or input pin transition until it reaches 0, at which time it startscounting up again.Each channel also includes a Match register that holds a smaller value than the Limitregister. In edge-aligned mode the channel’s outputs are switched whenever the TCmatches either the Match or Limit register, while in center-aligned mode they are switchedonly when it matches the Match register.So the Limit register controls the period of the outputs, while the Match register controlshow much of each period the outputs spend in each state. Having a small value in theLimit register minimizes “ripple” if the output is integrated into a voltage, and allows theMCPWM to control devices that operate at high speed.The “downside” of small values in the Limit register is that they reduce the resolution ofthe duty cycle controlled by the Match register. If you have 8 in the Limit register, theMatch register can only select the duty cycle among 0%, 12.5%, 25%, …, 87.5%, or100%. In general, the resolution of each step in the Match value is 1 divided by the Limitvalue.This trade-off between resolution and period/frequency is inherent in the design of pulsewidth modulators.