NXP Semiconductors LPC43 Series User Manual

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NXP Semiconductors LPC43 Series User Manual Manual pdf 1010 page image

UM10503 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.User manual Rev. 1.3 — 6 July 2012 1010 of 1269NXP Semiconductors UM10503Chapter 39: LPC43xx SSP0/139.7 Functional description39.7.1 Texas Instruments synchronous serial frame formatFigure 122 shows the 4-wire Texas Instruments synchronous serial frame formatsupported by the SSP module.For device configured as a master in this mode, CLK and FS are forced LOW, and thetransmit data line DX is tri-stated whenever the SSP is idle. Once the bottom entry of thetransmit FIFO contains data, FS is pulsed HIGH for one CLK period. The value to betransmitted is also transferred from the transmit FIFO to the serial shift register of thetransmit logic. On the next rising edge of CLK, the MSB of the 4-bit to 16-bit data frame isshifted out on the DX pin. Likewise, the MSB of the received data is shifted onto the DRpin by the off-chip serial slave device.Table 882: SSP DMA Control Register (DMACR - address 0x4008 3024 (SSP0), 0x400C 5024(SSP1)) bit descriptionBit Symbol Description Resetvalue0 RXDMAE Receive DMA Enable. When this bit is set to one 1, DMAfor the receive FIFO is enabled, otherwise receive DMA isdisabled.01 TXDMAE Transmit DMA Enable. When this bit is set to one 1, DMAfor the transmit FIFO is enabled, otherwise transmit DMAis disabled031:2 - Reserved, user software should not write ones to reservedbits. The value read from a reserved bit is not defined.NAa. Single frame transferb. Continuous/back-to-back frames transferFig 122. Texas Instruments Synchronous Serial Frame Format: a) Single and b) Continuous/back-to-back TwoFrames TransferCLKFSDX/DR4 to 16 bitsMSB LSBCLKFSDX/DR LSBMSB LSBMSB4 to 16 bits 4 to 16 bits