NXP Semiconductors LPC43 Series User Manual

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NXP Semiconductors LPC43 Series User Manual Manual pdf 341 page image

UM10503 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.User manual Rev. 1.3 — 6 July 2012 341 of 1269NXP Semiconductors UM10503Chapter 17: LPC43xx GPIO17.5.2.3 GPIO grouped interrupt port enable registersThe grouped interrupt port enable registers enable the pins which contribute to thegrouped interrupt. Each port n (n = 0 to 7) is associated with its own port enable register,and the values of all registers together determine which pins contribute to the groupedinterrupt.17.5.3 GPIO port register description17.5.3.1 GPIO port byte pin registersEach GPIO pin GPIOn[m] has a byte register in this address range. The byte pin registersof GPIO port 0 correspond to registers B0 to B31, the byte pin registers of GPIO port 1correspond to registers B32 to B63, etc.. Byte addresses are reserved for unused GPIOport pins (see Table 180).Software typically reads and writes bytes to access individual pins but also can read orwrite halfwords to sense or set the state of two pins, and read or write words to sense orset the state of four pins.Remark: To read the signal on the GPIO input, enable the input buffer in the syscon blockfor the corresponding pin (see Table 133 to Table 135).Table 197. GPIO grouped interrupt port polarity registers (PORT_POL, addresses 0x40088020 (PORT_POL0) to 0x4008 803C (PORT_POL7) (GROUP0 INT) and 0x4008 9020(PORT_POL0) to 0x4008 903C (PORT_POL7) (GROUP1 INT)) bit descriptionBit Symbol Description ResetvalueAccess31:0 POL Configure pin polarity of port n pins for group interrupt. Bit mcorresponds to pin GPIOn[m] of port n.0 = the pin is active LOW. If the level on this pin is LOW, thepin contributes to the group interrupt.1 = the pin is active HIGH. If the level on this pin is HIGH, thepin contributes to the group interrupt.1 -Table 198. GPIO grouped interrupt port n enable registers (PORT_ENA, addresses 0x40088040 (PORT_ENA0) to 0x4008 805C (PORT_ENA7) (GROUP0 INT) and 0x4008 9040(PORT_ENA0) to 0x4008 905C (PORT_ENA7) (GROUP1 INT)) bit descriptionBit Symbol Description ResetvalueAccess31:0 ENA Enable port n pin for group interrupt. Bit m corresponds to pinGPIOPn[m] of port n.0 = the port n pin is disabled and does not contribute to thegrouped interrupt.1 = the port n pin is enabled and contributes to the groupedinterrupt.0 -