NXP Semiconductors LPC43 Series User Manual

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NXP Semiconductors LPC43 Series User Manual Manual pdf 127 page image

UM10503 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.User manual Rev. 1.3 — 6 July 2012 127 of 1269NXP Semiconductors UM10503Chapter 11: LPC43xx Clock Generation Unit (CGU)The PLL contains three programmable dividers: pre-divider (N), feedback-divider (M) andpost-divider (P). The PLL contains a lock detector which measures the phase differencebetween the rising edges of the input and feedback clocks. Only when this difference issmaller than the so called “lock criterion” for more than seven consecutive input clockperiods, the lock output switches from low to high. A single too large phase differenceimmediately resets the counter and causes the lock signal to drop (if it was high).Requiring seven phase measurements in a row to be below a certain figure ensures thatthe lock detector will not indicate lock until both the phase and frequency of the input andfeedback clocks are very well aligned. This effectively prevents false lock indications, andthus ensures a glitch free lock signal.To avoid frequency hang-up the PLL contains a frequency limiter. This feature is built in toprevent the CCO from running too fast, this can occur if e.g. a wrong feedback-divider (M)ratio is applied to the PLL.Remark: The PLL0 does not use the direct binary representations of M, N, and P directly.Instead, encoded versions MDEC, NDEC, and PDEC of M, N, and P respectively.See Section 11.6.3.3 and Section 11.6.3.4 for how to obtain the encoded values for M, N,and P.11.7.4.3 Use of PLL0 operating modes11.7.4.3.1 Normal ModeMode 1 is the normal operating mode.The pre- and post-divider can be selected to give:Fig 27. PLL0 block diagramBypassCTRL[1]CLKOUTCLKIN32kHzIRCENET_RX_CLKENET_TX_CLKGP_CLKINCRYSTALPLL1IDIVAIDIVBIDIVCIDIVDIDIVECTRL[27:24]“1”N-DIVIDERNP_DIV[21:12]Direct InputCTRL[2]PFD Filter CCOQDCLKENCTRL[4]/2NP_DIV[6:0]P-DIVIDER/2M-DIVIDERMDIV[16:0]Direct OutputCTRL[3]Bandwidth Select P,I,RMDIV[31:17]Table 92. PLL0 operating modesPLL0_Mode bit settings:Mode PD CLKEN BYPASS DIRECTI DIRECTO FRM1: Normal 0 1 0 1/0 1/0 03: Power Down 1 x x x x x