NXP Semiconductors LPC43 Series User Manual

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NXP Semiconductors LPC43 Series User Manual Manual pdf 1120 page image

UM10503 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.User manual Rev. 1.3 — 6 July 2012 1120 of 1269NXP Semiconductors UM10503Chapter 43: LPC43xx I2C-bus interfaceAlthough the DATA_BUFFER register is primarily intended for use in monitor mode withthe ENA_SCL bit = ‘0’, it will be available for reading at any time under any mode ofoperation.43.7.10 I2C Mask registersThe four mask registers each contain seven active bits (7:1). Any bit in these registerswhich is set to ‘1’ will cause an automatic compare on the corresponding bit of thereceived address when it is compared to the ADRn register associated with that maskregister. In other words, bits in an ADRn register which are masked are not taken intoaccount in determining an address match.On reset, all mask register bits are cleared to ‘0’.The mask register has no effect on comparison to the General Call address (“0000000”).Bits(31:8) and bit(0) of the mask registers are unused and should not be written to. Thesebits will always read back as zeros.When an address-match interrupt occurs, the processor will have to read the data register(DAT) to determine what the received address was that actually caused the match.43.8 I2 C operating modesIn a given application, the I2 C block may operate as a master, a slave, or both. In the slavemode, the I2C hardware looks for any one of its four slave addresses and the General Calladdress. If one of these addresses is detected, an interrupt is requested. If the processorwishes to become the bus master, the hardware waits until the bus is free before themaster mode is entered so that a possible slave operation is not interrupted. If busarbitration is lost in the master mode, the I 2 C block switches to the slave modeimmediately and can detect its own slave address in the same serial transfer.Table 992. I2 C Data buffer register (DATA_BUFFER - address 0x400A 102C (I2C0) and0x400E 002C (I2C1)) bit descriptionBit Symbol Description Reset value7:0 Data This register holds contents of the 8 MSBs of the DAT shiftregister.031:8 - Reserved. The value read from a reserved bit is not defined. -Table 993. I2 C Mask registers (MASK - address 0x400A 1030 (MASK0) to 0x400A 103C(MASK3) (I2C0) and 0x400E 0030 (MASK0) to 0x400E 003C (MASK3) (I2C1)) bitdescriptionBit Symbol Description Reset value0 - Reserved. User software should not write ones to reserved bits.This bit reads always back as 0.07:1 MASK Mask bits. 0x0031:8 - Reserved. The value read from a reserved bit is not defined. -