NXP Semiconductors LPC43 Series User Manual

Contents

NXP Semiconductors LPC43 Series User Manual Manual pdf 118 page image

UM10503 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.User manual Rev. 1.3 — 6 July 2012 118 of 1269NXP Semiconductors UM10503Chapter 11: LPC43xx Clock Generation Unit (CGU)11.6.9 BASE_SAFE_CLK control registerThis register controls the BASE_SAFE_CLK to the watchdog oscillator. The only possibleclock source for this base clock is the IRC.11.6.10 BASE_USB0_CLK control registerThis register controls the BASE_USB0_CLK to the High-speed USB0. The only possibleclock source for this base clock is the PLL0USB output.28:24 CLK_SEL Clock-source selection. All other values arereserved.0x01 R/W0x00 32 kHz oscillator0x01 IRC (default)0x02 ENET_RX_CLK0x03 ENET_TX_CLK0x04 GP_CLKIN0x06 Crystal oscillator0x08 PLL0AUDIO0x09 PLL10x0C IDIVA31:29 - Reserved - -Table 83. IDIVE control register (IDIVE_CTRL, address 0x4005 0058) bit descriptionBit Symbol Value Description ResetvalueAccessTable 84. BASE_SAFE_CLK control register (BASE_SAFE_CLK, address 0x4005 005C) bitdescriptionBit Symbol Value Description ResetvalueAccess0 PD Output stage power down 0 R/W0 Output stage enabled (default)1 power-down10:1 - Reserved - -11 AUTOBLOCK Block clock automatically during frequencychange0 R/W0 Autoblocking disabled1 Autoblocking enabled23:12 - Reserved - -28:24 CLK_SEL Clock source selection. All other valuesare reserved.0x01 R/W0x01 IRC (default)31:29 - Reserved - -