UM10503 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.User manual Rev. 1.3 — 6 July 2012 1109 of 1269NXP Semiconductors UM10503Chapter 43: LPC43xx I2C-bus interface43.4 ApplicationsInterfaces to external I 2C standard parts, such as serial RAMs, LCDs, tone generators,other microcontrollers, etc.43.5 General descriptionA typical I2C-bus configuration is shown in Figure 158. Depending on the state of thedirection bit (R/W), two types of data transfers are possible on the I 2C-bus:• Data transfer from a master transmitter to a slave receiver. The first byte transmittedby the master is the slave address. Next follows a number of data bytes. The slavereturns an acknowledge bit after each received byte.• Data transfer from a slave transmitter to a master receiver. The first byte (the slaveaddress) is transmitted by the master. The slave then returns an acknowledge bit.Next follows the data bytes transmitted by the slave to the master. The master returnsan acknowledge bit after all received bytes other than the last byte. At the end of thelast received byte, a “not acknowledge” is returned. The master device generates allof the serial clock pulses and the START and STOP conditions. A transfer is endedwith a STOP condition or with a Repeated START condition. Since a RepeatedSTART condition is also the beginning of the next serial transfer, the I2 C bus will notbe released.The I2 C interface is byte oriented and has four operating modes: master transmitter mode,master receiver mode, slave transmitter mode and slave receiver mode.The I2 C interface complies with the entire I 2 C specification, supporting the ability to turnpower off to the processor without interfering with other devices on the same I 2 C-bus.Fig 158. I2 C-bus configurationOTHER DEVICE WITHI 2 C INTERFACEpull-upresistorOTHER DEVICE WITHI 2C INTERFACELPC43xxSDA SCLI 2C busSCLSDApull-upresistor