NXP Semiconductors LPC43 Series User Manual

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NXP Semiconductors LPC43 Series User Manual Manual pdf 477 page image

UM10503 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.User manual Rev. 1.3 — 6 July 2012 477 of 1269NXP Semiconductors UM10503Chapter 21: LPC43xx External Memory Controller (EMC)For example, for the refresh period of 16 μs, and a CCLK frequency of 50 MHz, thefollowing value must be programmed into this register:(16 x 10-6 x 50 x 10 6) / 16 = 50 or 0x32If auto-refresh through warm reset is requested (by setting the EMC_Reset_Disable bit),the timing of auto-refresh must be adjusted to allow a sufficient refresh rate when theclock rate is reduced during the wake-up period of a reset cycle. During this period, theEMC (and all other portions of the chip that are being clocked) run from the IRC oscillatorat 12 MHz. The IRC oscillator frequency must be used as the CCLK rate for refreshcalculations if auto-refresh through warm reset is requested.Note: The refresh cycles are evenly distributed. However, there might be slight variationswhen the auto-refresh command is issued depending on the status of the memorycontroller.21.7.6 Dynamic Memory Read Configuration registerThe DYNAMICREADCONFIG register configures the dynamic memory read strategy.This register must be modified during system initialization with a bit value RD  1. Thisregister is accessed with one wait state.Note: This register is used for all four dynamic memory chip selects. Therefore the worstcase value for all of the chip selects must be programmed.Remark: Choose command delay strategy (RD = 0x1) for SDRAM operation.See Section 15.4.9 for programming the delay value for the EMC_CLKn delay.Table 358. Dynamic Memory Refresh Timer register (DYNAMICREFRESH - address0x4000 5024) bit descriptionBit Symbol Description Resetvalue10:0 REFRESH Refresh timer.Indicates the multiple of 16 CCLKs between SDRAM refresh cycles.0x0 = Refresh disabled (POR reset value).0x1 - 0x7FF = n x16 = 16n CCLKs between SDRAM refresh cycles.For example:0x1 = 1 x 16 = 16 CCLKs between SDRAM refresh cycles.0x8 = 8 x 16 = 128 CCLKs between SDRAM refresh cycles031:11 - Reserved, user software should not write ones to reserved bits. Thevalue read from a reserved bit is not defined.-