NXP Semiconductors LPC43 Series User Manual

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NXP Semiconductors LPC43 Series User Manual Manual pdf 1110 page image

UM10503 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.User manual Rev. 1.3 — 6 July 2012 1110 of 1269NXP Semiconductors UM10503Chapter 43: LPC43xx I2C-bus interface43.5.1 I2C Fast-mode PlusFast-Mode Plus supports a 1 Mbit/sec transfer rate to communicate with the I 2C-busproducts which NXP Semiconductors is now providing.In order to use Fast-Mode Plus, the I2 C pins must be properly configured in the SFSI2C0register in the SYSCON block (see Table 137).43.6 Pin descriptionThe I2 C-bus pins must be configured through SYSCON registers for Standard/ Fast-modeor Fast-mode Plus.43.7 Register descriptionTable 979. I2 C-bus pin descriptionPin function Type DescriptionI2C0_SDA Input/Output I2 C data input/output. Open-drain output (for I 2C-buscompliance).I2C0_SCL Input/Output I2 C clock input/output. Open-drain output (for I 2C-buscompliance).I2C1_SDA Input/Output I2 C Serial Data. Uses standard I/O pins (Fast-mode only).I2C1_SCL Input/Output I2 C Serial Clock. Uses standard I/O pins (Fast-mode only).Table 980. Register overview: I2 C0 (base address 0x400A 1000)Name Access AddressoffsetDescription Resetvalue[1]ReferenceCONSET R/W 0x000 I2C Control Set Register. When a one is written to a bit ofthis register, the corresponding bit in the I2 C control register isset. Writing a zero has no effect on the corresponding bit inthe I 2C control register.0x00 Table 982STAT RO 0x004 I2C Status Register. During I 2C operation, this registerprovides detailed status codes that allow software todetermine the next action needed.0xF8 Table 983DAT R/W 0x008 I2C Data Register. During master or slave transmit mode,data to be transmitted is written to this register. During masteror slave receive mode, data that has been received may beread from this register.0x00 Table 984ADR0 R/W 0x00C I2C Slave Address Register 0. Contains the 7-bit slaveaddress for operation of the I 2C interface in slave mode, andis not used in master mode. The least significant bitdetermines whether a slave responds to the General Calladdress.0x00 Table 985SCLH R/W 0x010 SCH Duty Cycle Register High Half Word. Determines thehigh time of the I 2C clock.0x04 Table 986SCLL R/W 0x014 SCL Duty Cycle Register Low Half Word. Determines thelow time of the I 2C clock. SCLL and SCLH together determinethe clock frequency generated by an I 2 C master and certaintimes used in slave mode.0x04 Table 987