NXP Semiconductors LPC43 Series User Manual

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NXP Semiconductors LPC43 Series User Manual Manual pdf 336 page image

UM10503 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.User manual Rev. 1.3 — 6 July 2012 336 of 1269NXP Semiconductors UM10503Chapter 17: LPC43xx GPIO[1] “ext” in this table and subsequent tables indicates that the data read after reset depends on the state of the pin, which in turn maydepend on an external source.17.5.1 GPIO pin interrupts register description17.5.1.1 Pin interrupt mode registerFor each of the 8 pin interrupts selected in the PINTSELn registers (see Table 145 andTable 146), one bit in the ISEL register determines whether the interrupt is edge or levelsensitive.17.5.1.2 Pin interrupt level (rising edge) interrupt enable registerFor each of the 8 pin interrupts selected in the PINTSELn registers (see Table 145 andTable 146), one bit in the IENR register enables the interrupt depending on the pininterrupt mode configured in the ISEL register:• If the pin interrupt mode is edge sensitive (PMODE = 0), the rising edge interrupt isenabled.• If the pin interrupt mode is level sensitive (PMODE = 1), the level interrupt is enabled.The IENF register configures the active level (HIGH or LOW) for this interrupt.NOT5 WO 0x2314 Toggle port 5 NA word (32 bit) Table 207NOT6 WO 0x2318 Toggle port 6 NA word (32 bit) Table 207NOT7 WO 0x231C Toggle port 7 NA word (32 bit) Table 207Table 185. Register overview: GPIO port (base address 0x400F 4000)The highest pin number on each port depends on package size (see Table 180).Name Access AddressoffsetDescription ResetvalueWidth ReferenceTable 186. Pin interrupt mode register (ISEL, address 0x4008 7000) bit descriptionBit Symbol Description ResetvalueAccess7:0 PMODE Selects the interrupt mode for each pin interrupt. Bit nconfigures the pin interrupt selected in PINTSELn.0 = Edge sensitive1 = Level sensitive0 R/W31:8 - Reserved. - -Table 187. Pin interrupt level (rising edge) interrupt enable register (IENR, address 0x40087004) bit descriptionBit Symbol Description ResetvalueAccess7:0 ENRL Enables the rising edge or level interrupt for each pininterrupt. Bit n configures the pin interrupt selected inPINTSELn.0 = Disable rising edge or level interrupt.1 = Enable rising edge or level interrupt.0 R/W31:8 - Reserved. - -