NXP Semiconductors LPC43 Series User Manual

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NXP Semiconductors LPC43 Series User Manual Manual pdf 500 page image

UM10503 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.User manual Rev. 1.3 — 6 July 2012 500 of 126922.1 How to read this chapterThe SPIFI is available on all LPC43xx parts.22.2 Basic configurationThe SPIFI is configured as follows:• See Table 383 for clocking and power control.• The SPIFI is reset by the SPIFI_RST (reset # 53).Remark: All parts can use the SPIFI for booting. See Section 5.3.5.4.22.3 Features• Quad SPI Flash Interface (SPIFI) interface to external flash.• Transfer rates of up to SPIFI_CLK/2 bytes per second.• External flash is directly memory mapped for fast access.• Supports 1-, 2-, and 4-bit bi-directional serial protocols.• Half-duplex protocol compatible with various vendors and devices .• The SPIFI memory is accessible by the GPDMA.• Software driver library available on the LPCware web site.22.4 General descriptionThe SPI Flash Interface (SPIFI) allows low-cost serial flash memories to be connected tothe Cortex-M4 processor with little performance penalty compared to parallel flashdevices with higher pin count.Many serial flash devices use a half-duplex command-driven SPI protocol for device setupand initialization. Quad devices then use a half-duplex, command-driven 4-bit protocol fornormal operation. Different serial flash vendors and devices accept or require differentcommands and command formats. SPIFI provides sufficient flexibility to be compatiblewith common flash devices, and includes extensions to help insure compatibility withfuture devices.UM10503Chapter 22: LPC43xx SPI Flash Interface (SPIFI)Rev. 1.3 — 6 July 2012 User manualTable 383. SPIFI clocking and power controlBase clock Branch clock OperatingfrequencySPIFI AHB register clock BASE_M4_CLK CLK_M4_SPIFI up to204 MHzSPIFI serial clock input BASE_SPIFI_CLK SPIFI_CLK 120 MHz