NXP Semiconductors LPC43 Series User Manual

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NXP Semiconductors LPC43 Series User Manual Manual pdf 529 page image

UM10503 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.User manual Rev. 1.3 — 6 July 2012 529 of 1269NXP Semiconductors UM10503Chapter 23: LPC43xx USB0 Host/Device/OTG controller5:4 - - Reserved 0 RO6 FPR Force port resumeAfter the device has been in Suspended state for 5 ms or more, softwaremust set this bit to one to drive resume signaling before clearing. Thedevice controller will set this bit to one if a J-to-K transition is detected whilethe port is in the Suspended state. The bit will be cleared when the devicereturns to normal operation. When this bit transitions to a one because aJ-to-K transition detected, the Port Change Detect bit in the USBSTSregister is set to one as well.0 R/W0 No resume (K-state) detected/driven on port.1 Resume detected/driven on port.7 SUSP SuspendIn device mode, this is a read-only status bit .0 RO0 Port not in Suspended state1 Port in Suspended state8 PR Port resetIn device mode, this is a read-only status bit. A device reset from the USBbus is also indicated in the USBSTS register.0 RO0 Port is not in the reset state.1 Port is in the reset state.9 HSP High-speed statusRemark: This bit is redundant with bits 27:26 (PSPD) in this register. It isimplemented for compatibility reasons.0 RO0 Host/device connected to the port is not in High-speed mode.1 Host/device connected to the port is in High-speed mode.11:10 - - Not used in device mode.12 - - Not used in device mode.13 - - Reserved - -15:14 PIC1_0 Port indicator controlWriting to this field effects the value of the USB0_IND[1:0] pins.00 R/W0x0 Port indicators are off.0x1 amber0x2 green0x3 undefinedTable 419. Port Status and Control register in device mode (PORTSC1_D - address 0x4000 6184) bit descriptionBit Symbol Value Description ResetvalueAccess