NXP Semiconductors LPC43 Series User Manual

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NXP Semiconductors LPC43 Series User Manual Manual pdf 153 page image

UM10503 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.User manual Rev. 1.3 — 6 July 2012 153 of 1269NXP Semiconductors UM10503Chapter 13: LPC43xx Reset Generation Unit (RGU)Table 111. Reset output configurationReset outputgeneratorResetoutput#Reset source Parts of the device reset whenactivatedCORE_RST 0 external reset,BOD reset,WWDT time-outresetEntire chip including peripherals in thebattery-powered domain: CGU, powermanagement controller, general purposeregisters, alarm timer, parts of the CREGblock, and RTC.PERIPH_RST 1 CORE_RST All peripherals with reset sourcePERIPH_RST and MASTER_RSTMASTER_RST 2 PERIPH_RST All peripherals with reset sourceMASTER_RSTReserved 3 - -WWDT_RST 4 CORE_RST WWDT. No software reset.CREG_RST 5 CORE_RST Configuration register block, Event router,backup registers, RTC, alarm timer. Nosoftware reset.Reserved 6 - 7 - -BUS_RST 8 PERIPH_RST Buses; RGU, CCU, and CGU registers;memory controllers; bus bridges. Do notuse during normal operation.SCU_RST 9 PERIPH_RST System control unitReserved 10 - 12 - -M4_RST 13 MASTER_RST Cortex-M4 system resetReserved 14 - -Reserved 15 - -LCD_RST 16 MASTER_RST LCD controller resetUSB0_RST 17 MASTER_RST USB0 resetUSB1_RST 18 MASTER_RST USB1 resetDMA_RST 19 MASTER_RST DMA resetSDIO_RST 20 MASTER_RST SDIO resetEMC_RST 21 MASTER_RST External memory controller resetETHERNET_RST 22 MASTER_RST Ethernet resetReserved 23 - 24 - -FLASHA_RST 25 PERIPH_RST Flash bank A resetReserved 26 - -EEPROM_RST 27 PERIPH_RST EEPROM resetGPIO_RST 28 PERIPH_RST GPIO resetFLASHB_RST 29 PERIPH_RST Flash bank B resetReserved 30 - 31 - -TIMER0_RST 32 PERIPH_RST Timer0 resetTIMER1_RST 33 PERIPH_RST Timer1 resetTIMER2_RST 34 PERIPH_RST Timer2 resetTIMER3_RST 35 PERIPH_RST Timer3 resetRITIMER_RST 36 PERIPH_RST Repetitive Interrupt timer reset