NXP Semiconductors LPC43 Series User Manual

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NXP Semiconductors LPC43 Series User Manual Manual pdf 282 page image

UM10503 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.User manual Rev. 1.3 — 6 July 2012 282 of 1269NXP Semiconductors UM10503Chapter 15: LPC43xx System Control Unit (SCU)/ IO configuration15.3.1 Digital pin functionThe FUNC bits in the SFS registers control the function of each pin. Each pin can supportup to eight digital functions.Some pins support an additional analog function. If thefunction is GPIO, the DIR registers determine whether the pin is configured as an input oroutput (see Table 201). For any peripheral function, the pin direction is controlledautomatically depending on the pin’s functionality. The GPIO DIR registers do not affectperipheral functions.15.3.2 Digital pin modeThe EPUN and EPD bits (see Figure 32) in the SFS registers allow the selection of weakon-chip pull-up or pull-down resistors with a typical value of 50 k for each pin or theselection of the repeater mode.The possible on-chip resistor configurations are pull-up enabled, pull-down enabled, or nopull-up/pull-down. The default value is pull-up enabled.The repeater mode enables the pull-up resistor if the pin is at a logic HIGH and enablesthe pull-down resistor if the pin is at a logic LOW. This causes the pin to retain its lastknown state if it is configured as an input and is not driven externally. Repeater mode maytypically be used to prevent a pin from floating (and potentially using significant power if itfloats to an indeterminate state) if it is temporarily not driven.To select the repeater mode, enable both the pull-up and the pull-down resistor in the SFSregisters.Fig 32. Block diagram of the I/O padslew rate bit EHSpull-up enable bit EPUNpull-down enable bit EPDglitchfilteranalog I/OESDESDPINVDDIOVSSIOinput buffer enable bit EZIfilter select bit ZIFdata input to coredata output from coreenable output driver