NXP Semiconductors LPC43 Series User Manual

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NXP Semiconductors LPC43 Series User Manual Manual pdf 340 page image

UM10503 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.User manual Rev. 1.3 — 6 July 2012 340 of 1269NXP Semiconductors UM10503Chapter 17: LPC43xx GPIO17.5.1.10 Pin interrupt status registerReading this register returns ones for pin interrupts that are currently requesting aninterrupt. For pins identified as edge-sensitive in the Interrupt Select register, writing onesto this register clears both rising- and falling-edge detection for the pin. For level-sensitivepins, writing ones inverts the corresponding bit in the Active level register, thus switchingthe active level on the pin.17.5.2 GPIO GROUP0/GROUP1 interrupt register description17.5.2.1 Grouped interrupt control register17.5.2.2 GPIO grouped interrupt port polarity registersThe grouped interrupt port polarity registers determine how the polarity of each enabledpin contributes to the grouped interrupt. Each port n (n = 0 to 7) is associated with its ownport polarity register, and the values of all registers together determine the groupedinterrupt.Table 195. Pin interrupt status register (IST address 0x4008 7024) bit descriptionBit Symbol Description ResetvalueAccess7:0 PSTAT Pin interrupt status. Bit n returns the status, clears the edgeinterrupt, or inverts the active level of the pin selected inPINTSELn.Read 0: interrupt is not being requested for this interrupt pin.Write 0: no operation.Read 1: interrupt is being requested for this interrupt pin.Write 1 (edge-sensitive): clear rising- and falling-edgedetection for this pin.Write 1 (level-sensitive): switch the active level for this pin (inthe IENF register).0 R/W31:8 - Reserved. - -Table 196. GPIO grouped interrupt control register (CTRL, addresses 0x4008 8000 (GROUP0INT) and 0x4008 9000 (GROUP1 INT)) bit descriptionBit Symbol Value Description Reset value0 INT Group interrupt status. This bit is cleared by writing aone to it. Writing zero has no effect.00 No interrupt request is pending.1 Interrupt request is active.1 COMB Combine enabled inputs for group interrupt 00 OR functionality: A grouped interrupt is generatedwhen any one of the enabled inputs is active (basedon its programmed polarity).1 AND functionality: An interrupt is generated when allenabled bits are active (based on their programmedpolarity).2 TRIG Group interrupt trigger 00 Edge-triggered1 Level-triggered31:3 - - Reserved 0