NXP Semiconductors LPC43 Series User Manual

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NXP Semiconductors LPC43 Series User Manual Manual pdf 370 page image

UM10503 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.User manual Rev. 1.3 — 6 July 2012 370 of 1269NXP Semiconductors UM10503Chapter 18: LPC43xx Serial GPIO (SGPIO)18.7.1 ConcatenationSlices can be concatenated to increase the buffer size beyond REG_SS. This feature alsoenables creating PWM streams by implementing reverse catenation.Concatenation is set by register SGPIO_MUX_CFG. The field CONCAT_ENABLEenables this feature. When multiple slices are concatenated, this field should be set thesame for all involved slices. Field CONCAT_ORDER sets the concatenation size. For asize of zero, the self- loop mode, the slice output is routed back to the slice input. Thismode can be used to create a repeating data stream.Figure 38 shows which slices can be concatenated. Slices are ordered in four groups,starting with slice A, B, C and D. Each group consists of four concatenated slices. Forexample, the slice A input can be extended with three extra slices using slice I, E and J.Or for output mode, slice I can be extended by slice A, J, and E. Slices are furthermoreordered in four sub-groups starting with E, F, G and H. These sub-groups supportconcatenation of two slices. Slices A and B support concatenation of up to seven slices.If multiple slices are concatenated then the concat_order for those slices should beconsistent. For the above example, input slice A should be set as input(concat_enable=0). When concat_enable is not set, the concat_order value is a don'tcare. For slices I, E and J set concat_enable=1 and use concat_order =10 (4 slices).Concatenated slices should have consistent shift clock and bit shift settings (inSLICE_MUX_CFG). When k slices are concatenated, PRESET_POS should be set to0x20 x k - 1.