NXP Semiconductors LPC43 Series User Manual

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NXP Semiconductors LPC43 Series User Manual Manual pdf 348 page image

UM10503 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.User manual Rev. 1.3 — 6 July 2012 348 of 126918.1 How to read this chapterThe SGPIO is available on all LPC43xx parts. The 12-bit ADC is not available on partsLPC4350/30/20/10.18.2 Basic configurationThe SGPIO is configured as follows:• See Table 209 for clocking and power control.• The SGPIO is reset by the SGPIO_RST (reset # 57).• The SGPIO interrupt is connected to interrupt slot # 31 in the ARM Cortex-M4 NVIC.• SGPIO outputs SGPIO3 and SGPIO12 are connected through the GIMA to the eventrecorder, the timers, and the SCT (see Table 148). SGPIO3 and SGPIO12 alsosupport a divided-by-128 signal to the GIMA (SGPIO3_DIV and SGPIO12_DIV).• SGPIO outputs 10 and 12 can trigger the 12-bit ADC.• SGPIO outputs 14 and 15 can trigger a GPDMA request.18.3 Features• Each SGPIO input/output slice can be used to perform a serial to parallel or parallel toserial data conversion.• 16 SGPIO input/output slices each with a 32-bit FIFO can shift the input value from apin or an output value to a pin with every cycle of a shift clock.• Each slice is double-buffered.• Interrupt is generated on a full FIFO, shift clock, or pattern match.• Slices can be concatenated to increase buffer size.• Each slice has a 32-bit pattern match filter.UM10503Chapter 18: LPC43xx Serial GPIO (SGPIO)Rev. 1.3 — 6 July 2012 User manualTable 209. SGPIO clocking and power controlBase clock Branch clock OperatingfrequencyNotesSGPIO peripheralclock(SGPIO_CLOCK)BASE_PERIPH_CLKCLK_PERIPH_SGPIOup to204 MHzThis clock isasynchronous to themain clock and can befreely chosen to createa desired SGPIO datarate.