NXP Semiconductors LPC43 Series User Manual

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NXP Semiconductors LPC43 Series User Manual Manual pdf 1043 page image

UM10503 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.User manual Rev. 1.3 — 6 July 2012 1043 of 1269NXP Semiconductors UM10503Chapter 41: LPC43xx I2S interfaceData is read from the transmit FIFO after the falling edge of WS and will be transferred tothe transmit clock domain after the rising edge of WS. On the next falling edge of WS, theleft data will be loaded in the shift register and transmitted. On the following rising edge ofWS, the right data is loaded and transmitted.The receive channel will start receiving data after a change of WS. When WS becomeslow it expects this data to be left data, when WS is high received data is expected to beright data. Reception will stop when the bit counter has reached the limit set by theWORDWIDTH value. On the next change of WS the received data will be stored in theappropriate hold register. When complete data is available, it will be written into thereceive FIFO.41.7.2 I2S operating modesThe clocking and WS usage of the I2S interface is fully configurable. In addition to masterand slave modes, which are independently configurable for the transmitter and thereceiver, several different clock sources are possible, including variations that share theclock and/or WS between the transmitter and receiver. This last option allows using theI2S interface with fewer pins, typically four.Figure 134 provides an overview of the complete I2S interface. Specific operating modesare explained in Section 41.7.2.1 and Section 41.7.2.2.