NXP Semiconductors LPC43 Series User Manual

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NXP Semiconductors LPC43 Series User Manual Manual pdf 862 page image

UM10503 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.User manual Rev. 1.3 — 6 July 2012 862 of 1269NXP Semiconductors UM10503Chapter 29: LPC43xx Timer0/1/2/3Figure 97 shows a timer configured to stop and generate an interrupt on match. Theprescaler is again set to 2 and the match register set to 6. In the next clock after the timerreaches the match value, the timer enable bit in TCR is cleared, and the interruptindicating that a match occurred is generated.29.7.2 DMA operationDMA requests are generated by 0 to 1 transitions of the External Match 0 and 1 bits ofeach timer. In order to have an effect, the GPDMA must be configured and the relevanttimer DMA request selected as a DMA source via the CREG block, see Table 46.When a timer is initially set up to generate a DMA request, the request may already beasserted before a match condition occurs. An initial DMA request may be avoided byhaving software by write a one to the interrupt flag location, as if clearing a timer interrupt.See Section 29.6.1. A DMA request will be cleared automatically when it is acted upon bythe GPDMA controller.Fig 96. A timer cycle in which PR=2, MRx=6, and both interrupt and reset on match are enabled.PCLKprescalecounterinterrupttimercountertimer counterreset2222 0 0 0 01 1 1 14 5 6 0 1Fig 97. A timer Cycle in Which PR=2, MRx=6, and both interrupt and stop on match are enabledPCLKprescale counterinterrupttimer counterTCR[0](counter enable)22 0 014 5 61 0