UM10503 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.User manual Rev. 1.3 — 6 July 2012 878 of 1269NXP Semiconductors UM10503Chapter 30: LPC43xx Motor Control PWM (MOTOCONPWM)30.7.9.2 MCPWM Interrupt Enable set addressWriting ones to this write-only address sets the corresponding bits in INTEN, thusenabling interrupts.30.7.9.3 MCPWM Interrupt Enable clear addressWriting ones to this write-only address clears the corresponding bits in INTEN, thusdisabling interrupts.10 ICAP2 Capture interrupt for channel 2. 00 Interrupt disabled.1 Interrupt enabled.14:11 - Reserved. -15 ABORT Fast abort interrupt. 00 Interrupt disabled.1 Interrupt enabled.31:16 - Reserved. -Table 712. MCPWM Interrupt Enable read address (INTEN - 0x400A 0050) bit descriptionBit Symbol Value Description ResetvalueTable 713. MCPWM interrupt enable set register (INTEN_SET - address 0x400A 0054) bitdescriptionBit Symbol Description Resetvalue0 ILIM0_SET Writing a one sets the corresponding bit in INTEN, thus enablingthe interrupt.-1 IMAT0_SET Writing a one sets the corresponding bit in INTEN, thus enablingthe interrupt.-2 ICAP0_SET Writing a one sets the corresponding bit in INTEN, thus enablingthe interrupt.-3 - Reserved. -4 ILIM1_SET Writing a one sets the corresponding bit in INTEN, thus enablingthe interrupt.-5 IMAT1_SET Writing a one sets the corresponding bit in INTEN, thus enablingthe interrupt.-6 ICAP1_SET Writing a one sets the corresponding bit in INTEN, thus enablingthe interrupt.-7 - Reserved. -9 ILIM2_SET Writing a one sets the corresponding bit in INTEN, thus enablingthe interrupt.-10 IMAT2_SET Writing a one sets the corresponding bit in INTEN, thus enablingthe interrupt.-11 ICAP2_SET Writing a one sets the corresponding bit in INTEN, thus enablingthe interrupt.-14:12 - Reserved. -15 ABORT_SET Writing a one sets the corresponding bit in INTEN, thus enablingthe interrupt.-31:16 - Reserved. -