NXP Semiconductors LPC43 Series User Manual

Contents

NXP Semiconductors LPC43 Series User Manual Manual pdf 387 page image

UM10503 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.User manual Rev. 1.3 — 6 July 2012 387 of 1269NXP Semiconductors UM10503Chapter 19: LPC43xx General Purpose DMA (GPDMA) controllerSRCADDR0 R/W 0x100 DMA Channel 0 Source Address Register 0x0000 0000 Table 286DESTADDR0 R/W 0x104 DMA Channel 0 Destination Address Register 0x0000 0000 Table 287LLI0 R/W 0x108 DMA Channel 0 Linked List Item Register 0x0000 0000 Table 288CONTROL0 R/W 0x10C DMA Channel 0 Control Register 0x0000 0000 Table 289CONFIG0 R/W 0x110 DMA Channel 0 Configuration Register[1] 0x0000 0000 Table 290Channel 1 registersSRCADDR1 R/W 0x120 DMA Channel 1 Source Address Register 0x0000 0000 Table 286DESTADDR1 R/W 0x124 DMA Channel 1 Destination Address Register 0x0000 0000 Table 287LLI1 R/W 0x128 DMA Channel 1 Linked List Item Register 0x0000 0000 Table 288CONTROL1 R/W 0x12C DMA Channel 1 Control Register 0x0000 0000 Table 289CONFIG1 R/W 0x130 DMA Channel 1 Configuration Register[1] 0x0000 0000 Table 290Channel 2 registersSRCADDR2 R/W 0x140 DMA Channel 2 Source Address Register 0x0000 0000 Table 286DESTADDR2 R/W 0x144 DMA Channel 2 Destination Address Register 0x0000 0000 Table 287LLI2 R/W 0x148 DMA Channel 2 Linked List Item Register 0x0000 0000 Table 288CONTROL2 R/W 0x14C DMA Channel 2 Control Register 0x0000 0000 Table 289CONFIG2 R/W 0x150 DMA Channel 2 Configuration Register[1] 0x0000 0000 Table 290Channel 3 registersSRCADDR3 R/W 0x160 DMA Channel 3 Source Address Register 0x0000 0000 Table 286DESTADDR3 R/W 0x164 DMA Channel 3 Destination Address Register 0x0000 0000 Table 287LLI3 R/W 0x168 DMA Channel 3 Linked List Item Register 0x0000 0000 Table 288CONTROL3 R/W 0x16C DMA Channel 3 Control Register 0x0000 0000 Table 289CONFIG3 R/W 0x170 DMA Channel 3 Configuration Register[1] 0x0000 0000 Table 290Channel 4 registersSRCADDR4 R/W 0x180 DMA Channel 4 Source Address Register 0x0000 0000 Table 286DESTADDR4 R/W 0x184 DMA Channel 4 Destination Address Register 0x0000 0000 Table 287LLI4 R/W 0x188 DMA Channel 4 Linked List Item Register 0x0000 0000 Table 288CONTROL4 R/W 0x18C DMA Channel 4 Control Register 0x0000 0000 Table 289CONFIG4 R/W 0x190 DMA Channel 4 Configuration Register[1] 0x0000 0000 Table 290Channel 5 registersSRCADDR5 R/W 0x1A0 DMA Channel 5 Source Address Register 0x0000 0000 Table 286DESTADDR5 R/W 0x1A4 DMA Channel 5 Destination Address Register 0x0000 0000 Table 287LLI5 R/W 0x1A8 DMA Channel 5 Linked List Item Register 0x0000 0000 Table 288CONTROL5 R/W 0x1AC DMA Channel 5 Control Register 0x0000 0000 Table 289CONFIG5 R/W 0x1B0 DMA Channel 5 Configuration Register[1] 0x0000 0000 Table 290Channel 6 registersSRCADDR6 R/W 0x1C0 DMA Channel 6 Source Address Register 0x0000 0000 Table 286DESTADDR6 R/W 0x1C4 DMA Channel 6 Destination Address Register 0x0000 0000 Table 287LLI6 R/W 0x1C8 DMA Channel 6 Linked List Item Register 0x0000 0000 Table 288CONTROL6 R/W 01CC DMA Channel 6 Control Register 0x0000 0000 Table 289Table 271. Register overview: GPDMA (base address 0x4000 2000) …continuedName Access AddressoffsetDescription Reset value Reference