NXP Semiconductors LPC43 Series User Manual

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NXP Semiconductors LPC43 Series User Manual Manual pdf 135 page image

UM10503 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.User manual Rev. 1.3 — 6 July 2012 135 of 1269NXP Semiconductors UM10503Chapter 11: LPC43xx Clock Generation Unit (CGU)11.8.4 PLL0AUDIO settings for audio applications11.8.4.1 Using the fractional dividerTable 95 shows typical divider settings for the audio PLL0 with the fractional divider active.To use the fractional divider, follow these steps:1. Set bit SEL_EXT = 0 and PLLFRACT_REQ = 1 in the PLL0AUDIO_CTRL register(Table 75).2. Calculate NDEC, PDEC, and PLLFRACT_CTRL for the output frequency Fout.3. Write the calculated NDEC and PDEC values to the PLL0AUDIO_NP_DIV register.4. Write the calculated PLLFRACT_CTRL value to the PLL0AUDIOFRAC register.Table 94. PLL0 (for USB) settings for 480 MHz output clockFclkin [MHz] PLL0USB_MDIV PLL0USB_NP_DIVTable 72 Table 731 0x073E 56C9 0x0030 20622 0x073E 2DAD 0x0030 20623 0x0B3E 34B1 0x0030 20624 0x0E3E 7777 0x0030 20625 0x0D32 6667 0x0030 20626 0x0B2A 2A66 0x0030 20628 0x0820 6AAA 0x0030 206210 0x071A 7FAA 0x0030 206212 0x0616 7FFA 0x0030 206215 0x0512 3FFF 0x0030 206216 0x0410 1FFF 0x0030 206220 0x040E 03FF 0x0030 206224 0x030C 00FF 0x0030 2062Table 95. PLL0AUDIO divider settings for 12 MHz inputFs [kHz] Fout [MHz] Fcco [MHz] Error [Hz] NDEC PDEC PLL0AUDIO_NP_DIV PLLF0RACT_CTRLTable 77 Table 78128Fs192 24.576 540.672 1 514 29 0x0000201d 0x16872b96 12.288 417.792 1 1 3 0x00001003 0x1a1cac88.2 11.2896 338.688 1 0 24 0x00000018 0x070e5664 8.192 344.064 1 0 30 0x0000001e 0x072b0248 6.144 307.2 1 1 6 0x00001006 0x13333344.1 5.6448 282.24 1 1 6 0x00001006 0x11a3d7256Fs192 49.152 491.52 11 514 5 0x00002005 0x147ae196 24.576 540.672 1 514 29 0x0000201d 0x16872b88.2 22.5792 451.584 1 1 14 0x0000100e 0x1c395864 16.384 360.448 1 1 29 0x0000101d 0x16872b