NXP Semiconductors LPC43 Series User Manual

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NXP Semiconductors LPC43 Series User Manual Manual pdf 718 page image

UM10503 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.User manual Rev. 1.3 — 6 July 2012 718 of 1269NXP Semiconductors UM10503Chapter 26: LPC43xx Ethernet26.6.40 DMA Current host receive buffer address registerThe Current Host Receive Buffer Address register points to the current Receive Bufferaddress being read by the DMA.26.7 Functional description26.7.1 Power management blockThis section describes the power management (PMT) mechanisms supported by theMAC. PMT supports the reception of network (remote) wake-up frames and Magic Packetframes. PMT does not perform the clock gate function, but generates interrupts forwake-up frames and Magic Packets received by the MAC. The PMT block sits on thereceiver path of the MAC and is enabled with remote wake-up frame enable and MagicPacket enable. These enables are in the PMT Control and Status register and areprogrammed by the Application.When the power-down mode is enabled in the PMT, then all received frames are droppedby the core and they are not forwarded to the application. The core comes out of thepower down mode only when either a Magic Packet or a Remote Wake-up frame isreceived and the corresponding detection is enabled.26.7.1.1 Remote wake-up frame registersThe register WKUPFMFILTER_REG, address (0x028), loads the Wake-up Frame Filterregister. To load values in a Wake-up Frame Filter register, the entire register(WKUPFMFILTER_REG) must be written. The WKUPFMFILTER_REG register is loadedby sequentially loading the eight register values in address (0x028) forWKUPFMFILTER_REG0, WKUPFMFILTER_REG1,... WKUPFMFILTER_REG7,respectively. WKUPFMFILTER_REG is read in the same way.Remark: The internal counter to access the appropriate WKUPFMFILTER_REG isincremented when lane 3 (or lane 0 in big-endian) is accessed by the CPU. This should bekept in mind if you are accessing these registers in byte or half-word mode.Table 573. DMA Current host transmit buffer address register(DMA_CURHOST_TRANS_BUF, address 0x4001 1050) bit descriptionBit Symbol Description ResetvalueAccess31:0 HTB Host Transmit Buffer Address PointerCleared on Reset. Pointer updated by DMA duringoperation.0 ROTable 574. DMA Current host receive buffer address register (DMA_CURHOST_REC_BUF,address 0x4001 1054) bit descriptionBit Symbol Description ResetvalueAccess31:0 HRB Host Receive Buffer Address PointerCleared on Reset. Pointer updated by DMA duringoperation.0 RO