NXP Semiconductors LPC43 Series User Manual

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NXP Semiconductors LPC43 Series User Manual Manual pdf 1115 page image

UM10503 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.User manual Rev. 1.3 — 6 July 2012 1115 of 1269NXP Semiconductors UM10503Chapter 43: LPC43xx I2C-bus interface43.7.2 I2C Status registerEach I2C Status register reflects the condition of the corresponding I 2 C interface. The I 2 CStatus register is Read-Only.The three least significant bits are always 0. Taken as a byte, the status register contentsrepresent a status code. There are 26 possible status codes. When the status code is0xF8, there is no relevant information available and the SI bit is not set. All other 25 statuscodes correspond to defined I 2 C states. When any of these states entered, the SI bit willbe set. For a complete list of status codes, refer to tables from Table 998 to Table 1003.43.7.3 I2C Data registerThis register contains the data to be transmitted or the data just received. The CPU canread and write to this register only while it is not in the process of shifting a byte, when theSI bit is set. Data in DAT remains stable as long as the SI bit is set. Data in DAT is alwaysshifted from right to left: the first bit to be transmitted is the MSB (bit 7), and after a bytehas been received, the first bit of received data is located at the MSB of DAT.43.7.4 I2C Slave Address register 0This register is readable and writable and are only used when an I 2 C interface is set toslave mode. In master mode, this register has no effect. The LSB of ADR is the GeneralCall bit. When this bit is set, the General Call address (0x00) is recognized.If this register contains 0x00, the I2C will not acknowledge any address on the bus. Thisregister will be cleared to this disabled state on reset. See also Table 991.Table 983. I2 C Status register (STAT - address 0x400A 1004 (I2C0) and 0x400E 0004 (I2C1))bit descriptionBit Symbol Description Reset value2:0 - These bits are unused and are always 0. 07:3 Status These bits give the actual status information about the I2 Cinterface.0x1F31:8 - Reserved. The value read from a reserved bit is not defined. -Table 984. I2 C Data register (DAT - 0x400A 1008 (I2C0) and 0x400E 0008 (I2C1)) bitdescriptionBit Symbol Description Reset value7:0 Data This register holds data values that have been received or areto be transmitted.031:8 - Reserved. The value read from a reserved bit is not defined. -Table 985. I2 C Slave Address register 0 (ADR0 - address 0x400A 100C (I2C0) and0x400E 000C (I2C1)) bit descriptionBit Symbol Description Reset value0 GC General Call enable bit. 07:1 Address The I2 C device address for slave mode. 0x0031:8 - Reserved. The value read from a reserved bit is not defined. -