NXP Semiconductors LPC43 Series User Manual

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NXP Semiconductors LPC43 Series User Manual Manual pdf 1230 page image

UM10503 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.User manual Rev. 1.3 — 6 July 2012 1230 of 1269NXP Semiconductors UM10503Chapter 50: Supplementary informationdescription . . . . . . . . . . . . . . . . . . . . . . . . . . .342Table 200. GPIO port word pin registers (W, addresses0x400F 5000 (W0) to 0x400F 13FC (W255)) bitdescription . . . . . . . . . . . . . . . . . . . . . . . . . . .342Table 201. GPIO port direction register (DIR, addresses0x400F 6000 (DIR0) to 0x400F 601C (DIR7)) bitdescription . . . . . . . . . . . . . . . . . . . . . . . . . . .342Table 202. GPIO port mask register (MASK, addresses0x400F 6080 (MASK0) to 0x400F 609C (MASK7))bit description . . . . . . . . . . . . . . . . . . . . . . . .343Table 203. GPIO port pin register (PIN, addresses 0x400F6100 (PIN0) to 0x400F 611C (PIN7)) bitdescription . . . . . . . . . . . . . . . . . . . . . . . . . . .343Table 204. GPIO masked port pin register (MPIN, addresses0x400F 6180 (MPIN0) to 0x400F 619C (MPIN7))bit description . . . . . . . . . . . . . . . . . . . . . . . . .343Table 205. GPIO port set register (SET, addresses 0x400F6200 (SET0) to 0x400F 621C (SET7)) bitdescription . . . . . . . . . . . . . . . . . . . . . . . . . . .344Table 206. GPIO port clear register (CLR, addresses 0x400F6280 (CLR0) to 0x400F 629C (CLR7)) bitdescription . . . . . . . . . . . . . . . . . . . . . . . . . . .344Table 207. GPIO port toggle register (NOT, addresses0x400F 6300 (NOT0) to 0x400F 632C (NOT7)) bitdescription . . . . . . . . . . . . . . . . . . . . . . . . . . .344Table 208. Pin interrupt registers for edge- andlevel-sensitive pins . . . . . . . . . . . . . . . . . . . .346Table 209. SGPIO clocking and power control . . . . . . . .348Table 210. SGPIO pin description . . . . . . . . . . . . . . . . . .350Table 211. Register overview: SGPIO (base address 0x40101000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .351Table 212. Pin multiplexer configuration registers(OUT_MUX_CFG0 to 15, addresses 0x4010 1000to 0x4010 103C) bit description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .353Table 213. Output pin multiplexing . . . . . . . . . . . . . . . . .353Table 214. Output enable control . . . . . . . . . . . . . . . . . .354Table 215. SGPIO multiplexer configuration registers(SGPIO_MUX_CFG0 to 15, addresses 0x40100040 to 0x4010 007C) bit description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .355Table 216. SGPIO multiplexer . . . . . . . . . . . . . . . . . . . . .357Table 217. Slice multiplexer configuration registers(SLICE_MUX_CFG0 to 15, addresses 0x40101080 to 0x4010 10BC) bit description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .358Table 218. Slice data registers (REG0 to 15, addresses0x4010 10C0 to 0x4010 10FC) bit description . .359Table 219. Slice data shadow registers (REG_SS0 to 15,addresses 0x4010 110 to 0x4010 113C) bitdescription . . . . . . . . . . . . . . . . . . . . . . . . . . .359Table 220. Reload registers (PRESET0 to 15, addresses0x4010 1140 to 0x4010 117C) bit description 359Table 221. Down counter registers (COUNT0 to 15,addresses 0x4010 1180 to 0x4010 11BC) bitdescription . . . . . . . . . . . . . . . . . . . . . . . . . . .359Table 222. Position registers (POS0 to 15, addresses0x4010 11C0 to 0x4010 11FC) bit description . .360Table 223. Slice A mask register (MASK_A, address 0x40101200) bit description . . . . . . . . . . . . . . . . . . . 360Table 224. Slice H mask register (MASK_H, address 0x40101204) bit description . . . . . . . . . . . . . . . . . . . 360Table 225. Slice I mask register (MASK_I, address 0x40101208) bit description . . . . . . . . . . . . . . . . . . . 360Table 226. Slice P mask register (MASK_P, address 0x4010120C) bit description . . . . . . . . . . . . . . . . . . . 361Table 227. GPIO input status register (GPIO_INREG,address 0x4010 1210) bit description . . . . . . 361Table 228. GPIO output control register (GPIO_OUTREG,address 0x4010 1214) bit description . . . . . . 361Table 229. GPIO output enable register (GPIO_OENREG,address 0x4010 1218) bit description . . . . . . 361Table 230. Slice count enable register (CTRL_ENABLED,address 0x4010 121C) bit description . . . . . 362Table 231. Slice count disable register (CTRL_DISABLED,address 0x4010 1220) bit description . . . . . . 362Table 232. Shift clock interrupt clear mask register(CLR_EN_0, address 0x4010 1F00) bitdescription . . . . . . . . . . . . . . . . . . . . . . . . . . . 362Table 233. Shift clock interrupt set mask register(SET_EN_0, address 0x4010 1F04) bitdescription . . . . . . . . . . . . . . . . . . . . . . . . . . . 362Table 234. Shift clock interrupt enable register (ENABLE_0,address 0x4010 1F08) bit description . . . . . . 363Table 235. Shift clock interrupt status register (STATUS_0,address 0x4010 1F0C) bit description . . . . . 363Table 236. Shift clock interrupt clear status register(CLR_STATUS_0, address 0x4010 1F10) bitdescription . . . . . . . . . . . . . . . . . . . . . . . . . . . 363Table 237. Shift clock interrupt set status register(SET_STATUS_0, address 0x4010 1F14) bitdescription . . . . . . . . . . . . . . . . . . . . . . . . . . . 363Table 238. Exchange clock interrupt clear mask register(CLR_EN_1, address 0x4010 1F20) bitdescription . . . . . . . . . . . . . . . . . . . . . . . . . . . 364Table 239. Exchange clock interrupt set mask register(SET_EN_1, address 0x4010 1F24) bitdescription . . . . . . . . . . . . . . . . . . . . . . . . . . . 364Table 240. Exchange clock interrupt enable register(ENABLE_1, address 0x4010 1F28) bitdescription . . . . . . . . . . . . . . . . . . . . . . . . . . . 364Table 241. Exchange clock interrupt status register(STATUS_1, address 0x4010 1F2C) bitdescription . . . . . . . . . . . . . . . . . . . . . . . . . . . 364Table 242. Exchange clock interrupt clear status register(CLR_STATUS_1, address 0x4010 1F30) bitdescription . . . . . . . . . . . . . . . . . . . . . . . . . . . 365Table 243. Exchange clock interrupt set status register(SET_STATUS_1, address 0x4010 1F34) bitdescription . . . . . . . . . . . . . . . . . . . . . . . . . . . 365Table 244. Pattern match interrupt clear mask register(CLR_EN2, address 0x4010 1F40) bit description365Table 245. Pattern match interrupt set mask register