NXP Semiconductors LPC43 Series User Manual

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NXP Semiconductors LPC43 Series User Manual Manual pdf 858 page image

UM10503 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.User manual Rev. 1.3 — 6 July 2012 858 of 1269NXP Semiconductors UM10503Chapter 29: LPC43xx Timer0/1/2/329.6.9 Timer capture registers (CR0 - CR3)Each Capture register is associated with a device pin and may be loaded with the TimerCounter value when a specified event occurs on that pin. The settings in the CaptureControl Register register determine whether the capture function is enabled, and whethera capture event happens on the rising edge of the associated pin, the falling edge, or onboth edges.5 CAP1I Interrupt on CAPn.1 event 01 A CR1 load due to a CAPn.1 event will generate an interrupt.0 This feature is disabled.6 CAP2RE Capture on CAPn.2 rising edge 01 A sequence of 0 then 1 on CAPn.2 will cause CR2 to be loadedwith the contents of TC.0 This feature is disabled.7 CAP2FE Capture on CAPn.2 falling edge: 01 A sequence of 1 then 0 on CAPn.2 will cause CR2 to be loadedwith the contents of TC.0 This feature is disabled.8 CAP2I Interrupt on CAPn.2 event 01 A CR2 load due to a CAPn.2 event will generate an interrupt.0 This feature is disabled.9 CAP3RE Capture on CAPn.3 rising edge 01 A sequence of 0 then 1 on CAPn.3 will cause CR3 to be loadedwith the contents of TC.0 This feature is disabled.10 CAP3FE Capture on CAPn.3 falling edge 01 A sequence of 1 then 0 on CAPn.3 will cause CR3 to be loadedwith the contents of TC.0 This feature is disabled.11 CAP3I Interrupt on CAPn.3 event: 01 A CR3 load due to a CAPn.3 event will generate an interrupt.0 This feature is disabled.31:12 - Reserved, user software should not write ones to reserved bits.The value read from a reserved bit is not defined.NATable 691. Timer capture control registers (CCR - addresses 0x4008 4028 (TIMER0),0x4008 5020 (TIMER1), 0x400C 3028 (TIMER2), 0x400C 4028 (TIMER3)) bitdescription …continuedBit Symbol Value Description ResetvalueTable 692. Timer capture registers (CR[0:3], address 0x4008 402C (CR0) to 0x4008 4038(CR3) (TIMER0), 0x4008 502C (CR0) to 0x4008 5038 (CR3) (TIMER1), 0x400C 302C(CR0) to 0x400C 3038 (CR3) (TIMER2), 0x400C 402C (CR0) to 0x400C 4038 (CR3)(TIMER3)) bit descriptionBit Symbol Description Resetvalue31:0 CAP Timer counter capture value. 0