NXP Semiconductors LPC43 Series User Manual

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NXP Semiconductors LPC43 Series User Manual Manual pdf 1040 page image

UM10503 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.User manual Rev. 1.3 — 6 July 2012 1040 of 1269NXP Semiconductors UM10503Chapter 41: LPC43xx I2S interfacewith the jitter. The frequency averages out to exactly (7/17) / 2, but some clocks will be aslightly different length than their neighbors. It is possible to avoid jitter entirely bychoosing fractions such that X divides evenly into Y, such as 2/4, 2/6, 3/9, 1/N, etc.41.6.10 I2S Receive Clock Rate registerThe MCLK rate for the I2S receiver is determined by the values in the RXRATE register.The required RXRATE setting depends on the peripheral clock rate (PCLK_I2S =CLK_APB1_I2S) and the desired MCLK rate (such as 256 fs).The receiver MCLK rate is generated using a fractional rate generator, dividing down thefrequency of PCLK_I2S. Values of the numerator (X) and the denominator (Y) must bechosen to produce a frequency twice that desired for the receiver MCLK, which must bean integer multiple of the receiver bit clock rate. Fractional rate generators have someaspects that the user should be aware of when choosing settings. These are discussed inSection 41.6.9.1. The equation for the fractional rate generator is:I2S_RX_MCLK = PCLK_I2S * (X/Y) /2Note: If the value of X or Y is 0, then no clock is generated. Also, the value of Y must begreater than or equal to X.41.6.11 I2S Transmit Clock Bit Rate registerThe bit rate for the I2S transmitter is determined by the value of the TXBITRATE register.The value depends on the audio sample rate desired and the data size and format(stereo/mono) used. For example, a 48 kHz sample rate for 16-bit stereo data requires abit rate of 48 000 x 16 x 2 = 1.536 MHz.Table 907. I2S Receive Clock Rate register (RXRATE - address 0x400A 2024 (I2S0) and 0x400A 3024 (I2S1)) bitdescriptionBit Symbol Description Resetvalue7:0 Y_DIVIDER I2S receive MCLK rate denominator. This value is used to divide PCLK to produce thereceive MCLK. Eight bits of fractional divide supports a wide range of possibilities. A value of0 stops the clock.015:8 X_DIVIDER I2S receive MCLK rate numerator. This value is used to multiply PCLK by to produce thereceive MCLK. A value of 0 stops the clock. Eight bits of fractional divide supports a widerange of possibilities. Note: the resulting ratio X/Y is divided by 2.031:16 - Reserved, user software should not write ones to reserved bits. The value read from areserved bit is not defined.-Table 908. I2S Transmit Clock Rate register (TXBITRATE - address 0x400A 2028 (I2S0) and 0x400A 3028 (I2S1)) bitdescriptionBit Symbol Description Resetvalue5:0 TX_BITRATE I2S transmit bit rate. This value plus one is used to divide TX_MCLK to produce thetransmit bit clock.031:6 - Reserved, user software should not write ones to reserved bits. The value read from areserved bit is not defined.-