NXP Semiconductors LPC43 Series User Manual

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NXP Semiconductors LPC43 Series User Manual Manual pdf 1122 page image

UM10503 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.User manual Rev. 1.3 — 6 July 2012 1122 of 1269NXP Semiconductors UM10503Chapter 43: LPC43xx I2C-bus interface43.8.2 Master Receiver modeIn the master receiver mode, data is received from a slave transmitter. The transfer isinitiated in the same way as in the master transmitter mode. When the START conditionhas been transmitted, the interrupt service routine must load the slave address and thedata direction bit to the I2 C Data register (DAT), and then clear the SI bit. In this case, thedata direction bit (R/W) should be 1 to indicate a read.When the slave address and data direction bit have been transmitted and anacknowledge bit has been received, the SI bit is set, and the Status Register will show thestatus code. For master mode, the possible status codes are 0x40, 0x48, or 0x38. Forslave mode, the possible status codes are 0x68, 0x78, or 0xB0. For details, refer toTable 999.After a Repeated START condition, I2C may switch to the master transmitter mode.43.8.3 Slave Receiver modeIn the slave receiver mode, data bytes are received from a master transmitter. To initializethe slave receiver mode, write any of the Slave Address registers (ADR0-3) and write theI2C Control Set register (CONSET) as shown in Table 995.Fig 160. Format of Master Receiver modeFig 161. A Master Receiver switches to Master Transmitter after sending Repeated STARTDATAA = Acknowledge (SDA low)A = Not acknowledge (SDA high)S = START conditionP = STOP conditionS SLAVE ADDRESS RW=1 A DATA Pn bytes data receivedfrom Master to Slavefrom Slave to MasterA AA = Acknowledge (SDA low)A = Not acknowledge (SDA high)S = START conditionP = STOP conditionSLA = Slave AddressSr = Repeated START conditionDATAn bytes data transmittedFrom master to slaveFrom slave to masterA DATA A ASLA R Sr W PS SLA DATAAA