NXP Semiconductors LPC43 Series User Manual

Contents

NXP Semiconductors LPC43 Series User Manual Manual pdf 1143 page image

UM10503 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.User manual Rev. 1.3 — 6 July 2012 1143 of 1269NXP Semiconductors UM10503Chapter 43: LPC43xx I2C-bus interfacecauses the I2C block to enter the “not addressed” slave mode (a defined state) and toclear the STO flag (no other bits in CON are affected). The SDA and SCL lines arereleased (a STOP condition is not transmitted).43.10.6 Some special casesThe I2 C hardware has facilities to handle the following special cases that may occurduring a serial transfer:• Simultaneous Repeated START conditions from two masters• Data transfer after loss of arbitration• Forced access to the I 2 C-bus• I2C-bus obstructed by a LOW level on SCL or SDA• Bus error43.10.6.1 Simultaneous Repeated START conditions from two mastersA Repeated START condition may be generated in the master transmitter or masterreceiver modes. A special case occurs if another master simultaneously generates aRepeated START condition (see Figure 171). Until this occurs, arbitration is not lost byeither master since they were both transmitting the same data.If the I2C hardware detects a Repeated START condition on the I2 C-bus before generatinga Repeated START condition itself, it will release the bus, and no interrupt request isgenerated. If another master frees the bus by generating a STOP condition, the I2C blockwill transmit a normal START condition (state 0x08), and a retry of the total serial datatransfer can commence.Table 1004.Miscellaneous StatesStatusCode(STAT)Status of the I 2C-busand hardwareApplication software response Next action taken by I2C hardwareTo/From DAT To CONSTA STO SI AA0xF8 No relevant stateinformation available;SI = 0.No DAT action No CON action Wait or proceed current transfer.0x00 Bus error during MSTor selected slavemodes, due to anillegal START orSTOP condition. State0x00 can also occurwhen interferencecauses the I2 C blockto enter an undefinedstate.No DAT action 0 1 0 X Only the internal hardware is affected inthe MST or addressed SLV modes. In allcases, the bus is released and the I2 Cblock is switched to the not addressedSLV mode. STO is reset.