NXP Semiconductors LPC43 Series User Manual

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NXP Semiconductors LPC43 Series User Manual Manual pdf 994 page image

UM10503 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.User manual Rev. 1.3 — 6 July 2012 994 of 1269NXP Semiconductors UM10503Chapter 38: LPC43xx UART12 PE Parity Error.When the parity bit of a received character is in the wrong state, a parity erroroccurs. An LSR read clears LSR[2]. Time of parity error detection is dependent onFCR[0].Note: A parity error is associated with the character at the top of the UART1 RBRFIFO.00 Parity error status is inactive.1 Parity error status is active.3 FE Framing Error.When the stop bit of a received character is a logic 0, a framing error occurs. AnLSR read clears LSR[3]. The time of the framing error detection is dependent onFCR0. Upon detection of a framing error, the RX will attempt to resynchronize tothe data and assume that the bad stop bit is actually an early start bit. However, itcannot be assumed that the next received byte will be correct even if there is noFraming Error.Note: A framing error is associated with the character at the top of the UART1RBR FIFO.00 Framing error status is inactive.1 Framing error status is active.4 BI Break Interrupt.When RXD1 is held in the spacing state (all zeroes) for one full charactertransmission (start, data, parity, stop), a break interrupt occurs. Once the breakcondition has been detected, the receiver goes idle until RXD1 goes to markingstate (all ones). An LSR read clears this status bit. The time of break detection isdependent on FCR[0].Note: The break interrupt is associated with the character at the top of the UART1RBR FIFO.00 Break interrupt status is inactive.1 Break interrupt status is active.5 THRE Transmitter Holding Register Empty.THRE is set immediately upon detection of an empty UART1 THR and is clearedon a THR write.10 THR contains valid data.1 THR is empty.6 TEMT Transmitter Empty.TEMT is set when both THR and TSR are empty; TEMT is cleared when either theTSR or the THR contain valid data.10 THR and/or the TSR contains valid data.1 THR and the TSR are empty.7 RXFE Error in RX FIFO.LSR[7] is set when a character with a RX error such as framing error, parity erroror break interrupt, is loaded into the RBR. This bit is cleared when the LSRregister is read and there are no subsequent errors in the UART1 FIFO.00 RBR contains no UART1 RX errors or FCR[0]=0.1 UART1 RBR contains at least one UART1 RX error.31:8 - Reserved, the value read from a reserved bit is not defined. NATable 859: UART1 Line Status Register (LSR - address 0x4008 2014) bit descriptionBit Symbol Value Description Resetvalue