NXP Semiconductors LPC43 Series User Manual

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NXP Semiconductors LPC43 Series User Manual Manual pdf 523 page image

UM10503 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.User manual Rev. 1.3 — 6 July 2012 523 of 1269NXP Semiconductors UM10503Chapter 23: LPC43xx USB0 Host/Device/OTG controller23.6.7 Device address (DEVICEADDR - device) and Periodic List Base(PERIODICLISTBASE- host) registers23.6.7.1 Device modeThe upper seven bits of this register represent the device address. After any controllerreset or a USB reset, the device address is set to the default address (0). The defaultaddress will match all incoming addresses. Software shall reprogram the address afterreceiving a SET_ADDRESS descriptor.The USBADRA bit is used to accelerate the SET_ADDRESS sequence by allowing theDCD to preset the USBADR register bits before the status phase of the SET_ADDRESSdescriptor.23.6.7.2 Host modeThis 32-bit register contains the beginning address of the Periodic Frame List in thesystem memory. The host controller driver (HCD) loads this register prior to starting theschedule execution by the Host Controller. The memory structure referenced by this1 0 1 32 elements (128 bytes) 71 1 0 16 elements (64 bytes) 61 1 1 8 elements (32 bytes) 5Table 408. Number of bits used for the frame list indexUSBCMDbit 15USBCMDbit 3USBCMDbit 2Frame list size NTable 409. USB Device Address register in device mode (DEVICEADDR - address 0x4000 6154) bit descriptionBit Symbol Value Description ResetvalueAccess23:0 - Reserved 0 -24 USBADRA Device address advance0 Any write to USBADR are instantaneous.1 When the user writes a one to this bit at the same time or before USBADRis written, the write to USBADR fields is staged and held in a hiddenregister. After an IN occurs on endpoint 0 and is acknowledged, USBADRwill be loaded from the holding register.Hardware will automatically clear this bit on the following conditions:• IN is ACKed to endpoint 0. USBADR is updated from the stagingregister.• OUT/SETUP occurs on endpoint 0. USBADR is not updated.• Device reset occurs. USBADR is set to 0.Remark: After the status phase of the SET_ADDRESS descriptor, theDCD has 2 ms to program the USBADR field. This mechanism will ensurethis specification is met when the DCD can not write the device addresswithin 2 ms from the SET_ADDRESS status phase. If the DCD writes theUSBADR with USBADRA=1 after the SET_ADDRESS data phase (beforethe prime of the status phase), the USBADR will be programmed instantlyat the correct time and meet the 2 ms USB requirement.31:25 USBADR USB device address 0 R/W