NXP Semiconductors LPC43 Series User Manual

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NXP Semiconductors LPC43 Series User Manual Manual pdf 98 page image

UM10503 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.User manual Rev. 1.3 — 6 July 2012 98 of 1269NXP Semiconductors UM10503Chapter 11: LPC43xx Clock Generation Unit (CGU)– Integer divider A: maximum division factor = 4 (see Table 81).– Integer dividers B, C, D: maximum division factor = 16 (see Table 82).– Integer divider E: maximum division factor = 256 (see Table 83).The output stages select a clock source from the clock source bus for each base clock(see Table 65). Except for the base clocks to the WWDT (BASE_SAFE_CLK) and USB0(BASE_USB0_CLK), the clock source for each output stage can be any of the externaland internal clocks and oscillators directly or one of the PLL outputs or any of the outputsof the integer dividers.[1] Maximum frequency that guarantees stable operation of the LPC43xx.Table 64 shows all available input clock sources for each clock generator.Table 63. CGU0 base clocksNumber Name Frequency[1]Description0 BASE_SAFE_CLK 12 MHz Base safe clock (always on) for WWDT1 BASE_USB0_CLK 480 MHz Base clock for USB02 BASE_PERIPH_CLK 204 MHz Base clock for SGPIO peripheral3 BASE_USB1_CLK 204 MHz Base clock for USB14 BASE_M4_CLK 204 MHz System base clock for ARM Cortex-M4core and APB peripheral blocks #0 and #25 BASE_SPIFI_CLK 204 MHz Base clock for SPIFI6 BASE_SPI_CLK 204 MHz Base clock for SPI7 BASE_PHY_RX_CLK 75 MHz Base clock for Ethernet PHY Receiveclock8 BASE_PHY_TX_CLK 75 MHz Base clock for Ethernet PHY Transmitclock9 BASE_APB1_CLK 204 MHz Base clock for APB peripheral block # 110 BASE_APB3_CLK 204 MHz Base clock for APB peripheral block # 311 BASE_LCD_CLK 204 MHz Base clock for LCD12 BASE_VADC_CLK 204 MHz Base clock for VADC13 BASE_SDIO_CLK 204 MHz Base clock for SD/MMC14 BASE_SSP0_CLK 204 MHz Base clock for SSP015 BASE_SSP1_CLK 204 MHz Base clock for SSP116 BASE_UART0_CLK 204 MHz Base clock for UART017 BASE_UART1_CLK 204 MHz Base clock for UART118 BASE_UART2_CLK 204 MHz Base clock for UART219 BASE_UART3_CLK 204 MHz Base clock for UART320 BASE_OUT_CLK 204 MHz Base clock for CLKOUT pin24-21 - - Reserved25 BASE_APLL_CLK 204 MHz Base clock for audio PLL26 BASE_CGU_OUT0_CLK 204 MHz Base clock for CGU_OUT0 clock output27 BASE_CGU_OUT1_CLK 204 MHz Base clock for CGU_OUT1 clock output