NXP Semiconductors LPC43 Series User Manual

Contents

NXP Semiconductors LPC43 Series User Manual Manual pdf 709 page image

UM10503 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.User manual Rev. 1.3 — 6 July 2012 709 of 1269NXP Semiconductors UM10503Chapter 26: LPC43xx Ethernet6 RI Receive interruptThis bit indicates the completion of frame reception. Specific frame status informationhas been posted in the descriptor. Reception remains in the Running state.0 R/W7 RU Receive buffer unavailableThis bit indicates that the Next Descriptor in the Receive List is owned by the host andcannot be acquired by the DMA. Receive Process is suspended. To resumeprocessing Receive descriptors, the host should change the ownership of thedescriptor and issue a Receive Poll Demand command. If no Receive Poll Demand isissued, Receive Process resumes when the next recognized incoming frame isreceived. This bit is set only when the previous Receive Descriptor was owned by theDMA.0 R/W8 RPS Received process stoppedThis bit is asserted when the Receive Process enters the Stopped state.0 R/W9 RWT Receive watchdog timeoutThis bit is asserted when a frame with a length greater than 2,048 bytes is received(10,240 when Jumbo Frame mode is enabled).0 R/W10 ETI Early transmit interruptThis bit indicates that the frame to be transmitted was fully transferred to the MTLTransmit FIFO.0 R/W12:11 - Reserved 0 RO13 FBI Fatal bus error interruptThis bit indicates that a bus error occurred, as detailed in bits [25:23]. When this bit isset, the corresponding DMA engine disables all its bus accesses.0 R/W14 ERI Early receive interruptThis bit indicates that the DMA had filled the first data buffer of the packet. ReceiveInterrupt bit 6 in this register automatically clears this bit.0 R/WTable 566. DMA Status register (DMA_STAT, address 0x4001 1014) bit description …continuedBit Symbol Description ResetvalueAccess