NXP Semiconductors LPC43 Series User Manual

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NXP Semiconductors LPC43 Series User Manual Manual pdf 1020 page image

UM10503 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.User manual Rev. 1.3 — 6 July 2012 1020 of 1269NXP Semiconductors UM10503Chapter 40: LPC43xx SPI[1] Reset value reflects the data stored in used bits only. It does not include reserved bits content.40.6.1 SPI Control RegisterThe SPCR register controls the operation of SPI through the configuration bits settingshown in Table 886.TCR R/W 0x010 SPI Test Control register. For functional testingonly.0x00TSR R/W 0x014 SPI Test Status register. For functional testingonly.0x00- R/W 0x018 Reserved. -INT R/W 0x01C SPI Interrupt Flag. This register contains theinterrupt flag for the SPI interface.0x00Table 885. Register overview: SPI (base address 0x4010 0000)Name Access AddressoffsetDescription Resetvalue [1]Table 886: SPI Control Register (CR - address 0x4010 0000) bit descriptionBit Symbol Value Description Resetvalue1:0 - Reserved, user software should not write ones to reservedbits. The value read from a reserved bit is not defined.-2 BITENABLE 0 The SPI controller sends and receives 8 bits of data pertransfer.01 The SPI controller sends and receives the number of bitsselected by bits 11:8.3 CPHA Clock phase control determines the relationship betweenthe data and the clock on SPI transfers, and controls whena slave transfer is defined as starting and ending.00 Data is sampled on the first clock edge of SCK. A transferstarts and ends with activation and deactivation of theSSEL signal.1 Data is sampled on the second clock edge of the SCK. Atransfer starts with the first clock edge, and ends with thelast sampling edge when the SSEL signal is active.4 CPOL Clock polarity control. 00 SCK is active high.1 SCK is active low.5 MSTR Master mode select. 00 The SPI operates in Slave mode.1 The SPI operates in Master mode.6 LSBF LSB First controls which direction each byte is shifted whentransferred.00 SPI data is transferred MSB (bit 7) first.1 SPI data is transferred LSB (bit 0) first.