NXP Semiconductors LPC43 Series User Manual

Contents

NXP Semiconductors LPC43 Series User Manual Manual pdf 762 page image

UM10503 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.User manual Rev. 1.3 — 6 July 2012 762 of 126927.1 How to read this chapterThe LCD controller is available on part LPC4350.27.2 Basic configurationThe LCD controller is configured as follows:• See Table 597 for clocking and power control.• The LCD is reset by the LCD_RST (reset # 16).• The LCD interrupt is connected to interrupt slot # 7 in the NVIC.27.3 Features• AHB bus master interface to access frame buffer.• Setup and control via a separate AHB slave interface.• Dual 16-deep programmable 64-bit wide FIFOs for buffering incoming display data.• Supports single and dual-panel monochrome Super Twisted Nematic (STN) displayswith 4 or 8-bit interfaces.• Supports single and dual-panel color STN displays.• Supports Thin Film Transistor (TFT) color displays.• Programmable display resolution including, but not limited to: 320x200, 320x240,640x200, 640x240, 640x480, 800x600, and 1024x768.• Hardware cursor support for single-panel displays.• 15 gray-level monochrome, 3375 color STN, and 32K color palettized TFT support.• 1, 2, or 4 bits-per-pixel (bpp) palettized displays for monochrome STN.• 1, 2, 4, or 8 bpp palettized color displays for color STN and TFT.• 16 bpp true-color non-palettized, for color STN and TFT.• 24 bpp true-color non-palettized, for color TFT.• Programmable timing for different display panels.• 256 entry, 16-bit palette RAM, arranged as a 128x32-bit RAM.• Frame, line, and pixel clock signals.• AC bias signal for STN, data enable signal for TFT panels.• Supports little and big-endian, and Windows CE data formats.• LCD panel clock may be generated from the peripheral clock, or from a clock inputpin.UM10503Chapter 27: LPC43xx LCDRev. 1.3 — 6 July 2012 User manualTable 597. LCD clocking and power controlBase clock Branch clock Operating frequencyLCD register interface clock BASE_M4_CLK CLK_M4_LCD up to 204 MHz