NXP Semiconductors LPC43 Series User Manual

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NXP Semiconductors LPC43 Series User Manual Manual pdf 487 page image

UM10503 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.User manual Rev. 1.3 — 6 July 2012 487 of 1269NXP Semiconductors UM10503Chapter 21: LPC43xx External Memory Controller (EMC)3 PM Page mode.In page mode the EMC can burst up to four external accesses.Therefore devices with asynchronous page mode burst four orhigher devices are supported. Asynchronous page mode bursttwo devices are not supported and must be accessed normally.00 Disabled (POR reset value).1 Async page mode enabled (page length four).5:4 - - Reserved, user software should not write ones to reserved bits.The value read from a reserved bit is not defined.-6 PC Chip select polarity.The value of the chip select polarity on power-on reset is 0.00 Active LOW chip select.1 Active HIGH chip select.7 PB Byte lane state.The byte lane state bit, PB, enables different types of memory tobe connected. For byte-wide static memories the BLSn[3:0]signal from the EMC is usually connected to WE (write enable).In this case for reads all the BLSn[3:0] bits must be HIGH. Thismeans that the byte lane state (PB) bit must be LOW.16 bit wide static memory devices usually have the BLSn[3:0]signals connected to the UBn and LBn (upper byte and lowerbyte) signals in the static memory. In this case a write to aparticular byte must assert the appropriate UBn or LBn signalLOW. For reads, all the UB and LB signals must be assertedLOW so that the bus is driven. In this case the byte lane state(PB) bit must be HIGH.Remark: When PB is set to 0, the WE signal is undefined or 0.You must set PB to 1, to use the WE signal.00 For reads all the bits in BLSn[3:0] are HIGH. For writes therespective active bits in BLSn[3:0] are LOW (POR reset value).1 For reads the respective active bits in BLSn[3:0] are LOW. Forwrites the respective active bits in BLSn[3:0] are LOW.8 EW Extended wait.Extended wait (EW) uses the StaticExtendedWait register totime both the read and write transfers rather than theStaticWaitRd and StaticWaitWr registers. This enables muchlonger transactions.[1]00 Extended wait disabled (POR reset value).1 Extended wait enabled.18:9 - - Reserved, user software should not write ones to reserved bits.The value read from a reserved bit is not defined.-19 B Buffer enable[2]. 00 Buffer disabled (POR reset value).1 Buffer enabled.Table 375. Static Memory Configuration registers (STATICCONFIG[0:3], address 0x4000 5200(STATICCONFIG0), 0x4000 5220 (STATICCONFIG1), 0x4000 5240(STATICCONFIG2), 0x4000 5260 (STATICCONFIG3)) bit descriptionBit Symbol Value Description Resetvalue