NXP Semiconductors LPC43 Series User Manual

Contents

NXP Semiconductors LPC43 Series User Manual Manual pdf 1069 page image

UM10503 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.User manual Rev. 1.3 — 6 July 2012 1069 of 1269NXP Semiconductors UM10503Chapter 42: LPC43xx C_CAN42.6.1.2 CAN status registerTable 934. CAN status register (STAT, address 0x400E 2004 (C_CAN0) and 0x400A 4004 (C_CAN1)) bit descriptionBit Symbol Value Description ResetvalueAccess2:0 LEC Last error codeType of the last error to occur on the CAN bus.The LEC field holds acode which indicates the type of the last error to occur on the CAN bus.This field will be cleared to ‘0’ when a message has been transferred(reception or transmission) without error. The unused code ‘111’ may bewritten by the CPU to check for updates.000 R/W0x0 No error.0x1 Stuff error: More than 5 equal bits in a sequence have occurred in apart of a received message where this is not allowed.0x2 Form error: A fixed format part of a received frame has the wrongformat.0x3 AckError: The message this CAN core transmitted was notacknowledged.0x4 Bit1Error: During the transmission of a message (with the exception ofthe arbitration field), the device wanted to send a HIGH/recessive level(bit of logical value ‘1’), but the monitored bus value wasLOW/dominant.0x5 Bit0Error: During the transmission of a message (or acknowledge bit,or active error flag, or overload flag), the device wanted to send aLOW/dominant level (data or identifier bit logical value ‘0’), but themonitored Bus value was HIGH/recessive. During busoff recovery thisstatus is set each time asequence of 11 HIGH/recessive bits has been monitored. This enablesthe CPU to monitor the proceeding of the busoff recovery sequence(indicating the bus is not stuck at LOW/dominant or continuouslydisturbed).0x6 CRCError: The CRC checksum was incorrect in the message received.0x7 Unused: No CAN bus event was detected (written by the CPU).3 TXOK Transmitted a message successfullyThe CPU must reset this bit. It is never reset by the CAN controller.0 R/W0 Since this bit must be reset by the CPU, no message has beensuccessfully transmitted.1 Since this bit was last reset by the CPU, a message has beensuccessfully transmitted (error free and acknowledged by at least oneother node).4 RXOK Received a message successfullyThe CPU must reset this bit. It is never reset by the CAN controller.0 R/W0 Since this bit was last reset by the CPU, no message has beensuccessfully received.1 Since this bit was last set to zero by the CPU, a message has beensuccessfully received independent of the result of acceptance filtering.