NXP Semiconductors LPC43 Series User Manual

Contents

NXP Semiconductors LPC43 Series User Manual Manual pdf 870 page image

UM10503 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.User manual Rev. 1.3 — 6 July 2012 870 of 1269NXP Semiconductors UM10503Chapter 30: LPC43xx Motor Control PWM (MOTOCONPWM)30.7.2 PWM Capture Control register30.7.2.1 MCPWM Capture Control read addressThe MCCAPCON register controls detection of events on the MCI0-2 inputs for allMCPWM channels. Any of the three MCI inputs can be used to trigger a capture event onany or all of the three channels. This address is read-only, but the underlying register canbe modified by writing to addresses CAPCON_SET and CAPCON_CLR.4 DISUP0_CLR Writing a one clears the corresponding bit in the CON register. -7:5 - Writing a one clears the corresponding bit in the CON register. -8 RUN1_CLR Writing a one clears the corresponding bit in the CON register. -9 CENTER1_CLR Writing a one clears the corresponding bit in the CON register. -10 POLA1_CLR Writing a one clears the corresponding bit in the CON register. -11 DTE1_CLR Writing a one clears the corresponding bit in the CON register. -12 DISUP1_CLR Writing a one clears the corresponding bit in the CON register. -15:13- Writing a one clears the corresponding bit in the CON register. -16 RUN2_CLR Writing a one clears the corresponding bit in the CON register. -17 CENTER2_CLR Writing a one clears the corresponding bit in the CON register. -18 POLA2_CLR Writing a one clears the corresponding bit in the CON register. -19 DTE2_CLR Writing a one clears the corresponding bit in the CON register. -20 DISUP2_CLR Writing a one clears the corresponding bit in the CON register. -28:21- Writing a one clears the corresponding bit in the CON register. -29 INVBDC_CLR Writing a one clears the corresponding bit in the CON register. -30 ACMOD_CLR Writing a one clears the corresponding bit in the CON register. -31 DCMODE_CLR Writing a one clears the corresponding bit in the CON register.Table 701. MCPWM Control clear address (CON_CLR - 0x400A 0008) bit descriptionBit Symbol Description ResetvalueTable 702. MCPWM Capture Control read address (CAPCON - 0x400A 000C) bit descriptionBit Symbol Description Resetvalue0 CAP0MCI0_RE A 1 in this bit enables a channel 0 capture event on a rising edge on MCI0. 01 CAP0MCI0_FE A 1 in this bit enables a channel 0 capture event on a falling edge on MCI0. 02 CAP0MCI1_RE A 1 in this bit enables a channel 0 capture event on a rising edge on MCI1. 03 CAP0MCI1_FE A 1 in this bit enables a channel 0 capture event on a falling edge on MCI1. 04 CAP0MCI2_RE A 1 in this bit enables a channel 0 capture event on a rising edge on MCI2. 05 CAP0MCI2_FE A 1 in this bit enables a channel 0 capture event on a falling edge on MCI2. 06 CAP1MCI0_RE A 1 in this bit enables a channel 1 capture event on a rising edge on MCI0. 07 CAP1MCI0_FE A 1 in this bit enables a channel 1 capture event on a falling edge on MCI0. 08 CAP1MCI1_RE A 1 in this bit enables a channel 1 capture event on a rising edge on MCI1. 09 CAP1MCI1_FE A 1 in this bit enables a channel 1 capture event on a falling edge on MCI1. 010 CAP1MCI2_RE A 1 in this bit enables a channel 1 capture event on a rising edge on MCI2. 0