NXP Semiconductors LPC43 Series User Manual

Contents

NXP Semiconductors LPC43 Series User Manual Manual pdf 292 page image

UM10503 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.User manual Rev. 1.3 — 6 July 2012 292 of 1269NXP Semiconductors UM10503Chapter 15: LPC43xx System Control Unit (SCU)/ IO configuration15.4.2 Pin configuration registers for high-drive pinsEach digital pin and each clock pin on the LPC43xx have an associated pin configurationregister which determines the pin’s function and electrical characteristics. The assignedfunctions for each pin are listed in .The pin configuration registers for high-drive pins control the following pins:• P1_17• P2_3 to P2_5Table 133. Pin configuration registers for normal-drive pins (SFS, address 0x4008 6000(SPSP0_0) to 0x4008 67AC (SFSPF_11)) bit descriptionBit Symbol Value Description ResetvalueAccess2:0 MODE Select pin function. 0 R/W0x0 Function 0 (default)0x1 Function 10x2 Function 20x3 Function 30x4 Function 40x5 Function 50x6 Function 60x7 Function 73 EPD Enable pull-down resistor at pad. 0 R/W0 Disable pull-down.1 Enable pull-down.Enable both pull-downresistor and pull-up resistor for repeatermode.4 EPUN Disable pull-up resistor at pad. By default,the pull-up resistor is enabled at reset.0 R/W0 Enable pull-up. Enable both pull-downresistor and pull-up resistor for repeatermode.1 Disable pull-up.5 EHS Select Slew rate. 0 R/W0 Slow (low noise with medium speed)1 Fast (medium noise with fast speed)6 EZI Input buffer enable. The input buffer isdisabled by default at reset and must beenabled for receiving.0 R/W0 Disable input buffer1 Enable input buffer7 ZIF Input glitch filter. Disable the input glitch filterfor clocking signals higher than 30 MHz.0 R/W0 Enable input glitch filter1 Disable input glitch filter31:8 - Reserved - -