NXP Semiconductors LPC43 Series User Manual

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NXP Semiconductors LPC43 Series User Manual Manual pdf 826 page image

UM10503 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.User manual Rev. 1.3 — 6 July 2012 826 of 1269NXP Semiconductors UM10503Chapter 28: LPC43xx State Configurable Timer (SCT)28.6.13 SCT conflict resolution registerThe registers OUTPUTSETn (Section 28.6.25) and OUTPUTCLn (Section 28.6.26) allowboth setting and clearing to be indicated for an output in the same clock cycle, even for thesame event. This SCT conflict resolution register resolves this conflict.To enable an event to toggle an output, set the OnRES value to 0x3 in this register, andset the event bits in both the Set and Clear registers.25:24SETCLR12 Set/clear operation on output 12. Value 0x3 is reserved. Do not program this value. 00x0 Set and clear do not depend on any counter.0x1 Set and clear are reversed when counter L or the unified counter is counting down.0x2 Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.27:26SETCLR13 Set/clear operation on output 13. Value 0x3 is reserved. Do not program this value. 00x0 Set and clear do not depend on any counter.0x1 Set and clear are reversed when counter L or the unified counter is counting down.0x2 Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.29:28SETCLR14 Set/clear operation on output 14. Value 0x3 is reserved. Do not program this value. 00x0 Set and clear do not depend on any counter.0x1 Set and clear are reversed when counter L or the unified counter is counting down.0x2 Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.31:30SETCLR15 Set/clear operation on output 15. Value 0x3 is reserved. Do not program this value. 00x0 Set and clear do not depend on any counter.0x1 Set and clear are reversed when counter L or the unified counter is counting down.0x2 Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1.Table 658. SCT bidirectional output control register (OUTPUTDIRCTRL - address 0x4000 0054) bit descriptionBit Symbol ValueDescription ResetvalueTable 659. SCT conflict resolution register (RES - address 0x4000 0058) bit descriptionBit Symbol Value Description Resetvalue1:0 O0RES Effect of simultaneous set and clear on output 0. 00x0 No change.0x1 Set output (or clear based on the SETCLR0 field).0x2 Clear output (or set based on the SETCLR0 field).0x3 Toggle output.3:2 O1RES Effect of simultaneous set and clear on output 1. 00x0 No change.0x1 Set output (or clear based on the SETCLR1 field).0x2 Clear output (or set based on the SETCLR1 field).0x3 Toggle output.