NXP Semiconductors LPC43 Series User Manual

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NXP Semiconductors LPC43 Series User Manual Manual pdf 283 page image

UM10503 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.User manual Rev. 1.3 — 6 July 2012 283 of 1269NXP Semiconductors UM10503Chapter 15: LPC43xx System Control Unit (SCU)/ IO configuration15.3.3 Input bufferTo be able to receive a digital signal, the input buffer must be enabled through bit EZI inthe pin configuration registers (see Figure 32). By default, the input buffer is disabled.For pads that support both a digital and an analog function, the input buffer must bedisabled before enabling the analog function (see Section 15.4.6 to Section 15.4.8).15.3.4 Programmable glitch filterAll digital pins support a programmable glitch filter (bit ZIF), which can be switched on oroff (see Figure 32). By default, the glitch filter is on. The glitch filter should be disabled forclocking signals with frequencies higher than 30 MHz.15.3.5 Programmable slew rateNormal-drive and high-speed pins support a programmable slew rate (bit EHS) to selectbetween lower noise and speed or higher noise and speed (see Figure 32). The typicalfrequencies supported are 50 MHz/80 MHz for normal-drive pins and 75 MHz/204 MHz forhigh-speed pins.15.3.6 High-speed pinsThe clock pins CLK0 to CLK3 and P3_3 support a programmable high-speed output withtypical frequencies of 75 MHz or 204 MHz depending on the slew rate setting (seeSection 15.3.5).15.3.7 High-drive pinsSelected pins (see Section 15.4.2) support a high-drive output with four programmablelevels.High-drive pins support the programmable glitch filter but not the programmable slew rate.15.3.8 I2C0-bus pinsThe SFSI2C0 register (Table 137) allows to configure different modes for I 2 C0-businterface:• Standard mode/Fast-mode I 2 C with an open-drain output according to the I2 C-busspecification. This is the default mode.• Fast-mode Plus mode with an open-drain output according to the I2 C-busspecification.The I2C0 pins use a programmable glitch filter (bit ZIF).Remark: The input buffer must be enabled for the I2C0 pins SDA and SCL for properoperation.15.3.9 USB1 USB1_DP/USB1_DM pinsThe input signal to the USB1 is controlled by the SFSUSB register (Table 136). TheUSB_ESEA bit in this register must be set to one to enable the USB1 block.