NXP Semiconductors LPC43 Series User Manual

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NXP Semiconductors LPC43 Series User Manual Manual pdf 530 page image

UM10503 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.User manual Rev. 1.3 — 6 July 2012 530 of 1269NXP Semiconductors UM10503Chapter 23: LPC43xx USB0 Host/Device/OTG controller19:16 PTC3_0 Port test controlAny value other than 0000 indicates that the port is operating in test mode.The FORCE_ENABLE_FS and FORCE ENABLE_LS are extensions to thetest mode support specified in the EHCI specification. Writing the PTC fieldto any of the FORCE_ENABLE_HS/FS/LS values will force the port intothe connected and enabled state at the selected speed. Writing the PTCfield back to TEST_MODE_DISABLE will allow the port state machines toprogress normally from that point. Values 0111 to 1111 are not valid.0000 R/W0x0 TEST_MODE_DISABLE0x1 J_STATE0x2 K_STATE0x3 SE0 (host)/NAK (device)0x4 Packet0x5 FORCE_ENABLE_HS0x6 FORCE_ENABLE_FS20 - - Not used in device mode. This bit is always 0 in device mode. 0 -21 - - Not used in device mode. This bit is always 0 in device mode. 0 -22 - Not used in device mode. This bit is always 0 in device mode. 0 -23 PHCD PHY low power suspend - clock disable (PLPSCD)In device mode, The PHY can be put into Low Power Suspend – ClockDisable when the device is not running (USBCMD Run/Stop = 0) or thehost has signaled suspend (PORTSC SUSPEND = 1). Low power suspendwill be cleared automatically when the host has signaled resume. Beforeforcing a resume from the device, the device controller driver must clearthis bit.0 R/W0 Writing a 0 enables the PHY clock. Reading a 0 indicates the status of thePHY clock (enabled).1 Writing a 1 disables the PHY clock. Reading a 1 indicates the status of thePHY clock (disabled).24 PFSC Port force full speed connect 0 R/W0 Port connects at any speed.1 Writing this bit to a 1 will force the port to only connect at full speed. Itdisables the chirp sequence that allows the port to identify itself asHigh-speed. This is useful for testing FS configurations with a HS host, hubor device.25 - - Reserved27:26 PSPD Port speedThis register field indicates the speed at which the port is operating.0 RO0x0 Full-speed0x1 invalid in device mode0x2 High-speed31:28 - - Reserved - -Table 419. Port Status and Control register in device mode (PORTSC1_D - address 0x4000 6184) bit descriptionBit Symbol Value Description ResetvalueAccess