NXP Semiconductors LPC43 Series User Manual

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NXP Semiconductors LPC43 Series User Manual Manual pdf 581 page image

UM10503 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.User manual Rev. 1.3 — 6 July 2012 581 of 1269NXP Semiconductors UM10503Chapter 23: LPC43xx USB0 Host/Device/OTG controller23.11 USB power optimizationThe USB-HS core is a fully synchronous static design. Applications that transfer moredata or use a greater number of packets to be sent will consume a greater amount ofpower.The USB power consumption can be controlled by disabling the USB clocks and disablingthe High-speed PHY (see Section 23.2).A device may go into the Suspended state either autonomously by disconnecting from theUSB, or in response to USB suspend signaling.23.11.1 USB power statesThe USB provides a mechanism to place segments of the USB or the entire USB into alow-power Suspended state. USB devices are required to respond to a 3ms lack of activityon the USB bus by going into a Suspended state. In the USB-HS core software is notifiedof the suspend condition via the transition of the SUSP bit in the PORTSC1 register.Optionally an interrupt can be generated which is controlled by the port change DetectEnable bit in the USBINTR control register. Software then has 7 ms to transition a buspowered device into the Suspended state. In the Suspended state, a USB device has amaximum USB bus power budget of 2.5 mA. In general, to achieve that level of powerconservation, most of the device circuits will need to be switched off, or clock at anextremely low frequency. This can be accomplished by suspending the clock.The implementation of low power states in the USB-HS core is dependent on the use ofthe device role (host or peripheral), whether the device is bus powered, and the selectedclock architecture of the core.Bus powered peripheral devices are required by the USB specification to support a lowpower Suspended state. Self powered peripheral devices and hosts set their own powermanagement strategies based on their system level requirements.Before the system clock is suspended or set to a frequency that is below the operationalfrequency of the USB-HS core, the core must be moved from the operational state to alow power state.23.11.2 Device power statesA bus powered peripheral device must move through the power states as directed by thehost. Optionally autonomously directed low power states may be implemented.