NXP Semiconductors LPC43 Series User Manual

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NXP Semiconductors LPC43 Series User Manual Manual pdf 860 page image

UM10503 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.User manual Rev. 1.3 — 6 July 2012 860 of 1269NXP Semiconductors UM10503Chapter 29: LPC43xx Timer0/1/2/329.6.11 Timer count control registersThe Count Control Register (CTCR) is used to select between Timer and Counter mode,and in Counter mode to select the pin and edge(s) for counting.When Counter Mode is chosen as a mode of operation, the CAP input (selected by theCTCR bits 3:2) is sampled on every rising edge of the PCLK clock. After comparing twoconsecutive samples of this CAP input, one of the following four events is recognized:rising edge, falling edge, either of edges or no changes in the level of the selected CAPinput. Only if the identified event corresponds to the one selected by bits 1:0 in the CTCRregister, the Timer Counter register will be incremented.9:8 EMC2 External Match Control 2. Determines the functionality ofExternal Match 2.000x0 Do Nothing.0x1 Clear the corresponding External Match bit/output to 0(MATn.m pin is LOW if pinned out).0x2 Set the corresponding External Match bit/output to 1 (MATn.mpin is HIGH if pinned out).0x3 Toggle the corresponding External Match bit/output.11:10 EMC3 External Match Control 3. Determines the functionality ofExternal Match 3.000x0 Do Nothing.0x1 Clear the corresponding External Match bit/output to 0(MATn.m pin is LOW if pinned out).0x2 Set the corresponding External Match bit/output to 1 (MATn.mpin is HIGH if pinned out).0x3 Toggle the corresponding External Match bit/output.31:12 - Reserved, user software should not write ones to reserved bits.The value read from a reserved bit is not defined.NATable 694. External Match ControlEMR[11:10], EMR[9:8],EMR[7:6], or EMR[5:4]Function00 Do Nothing.01 Clear the corresponding External Match bit/output to 0 (MATn.m pin isLOW if pinned out).10 Set the corresponding External Match bit/output to 1 (MATn.m pin isHIGH if pinned out).11 Toggle the corresponding External Match bit/output.Table 693. Timer external match registers (EMR - addresses 0x4008 403C (TIMER0),0x4008 503C (TIMER1), 0x400C 303C (TIMER2), 0x400C 403C (TIMER3)) bitdescriptionBit Symbol Value Description Resetvalue